Searched refs:gb_addr_config_fields (Results 1 – 8 of 8) sorted by relevance
218 adev->gfx.config.gb_addr_config_fields.num_pipes; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()220 adev->gfx.config.gb_addr_config_fields.num_banks; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()222 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()224 adev->gfx.config.gb_addr_config_fields.num_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()226 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()455 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in amdgpu_dm_plane_add_gfx9_modifiers()457 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in amdgpu_dm_plane_add_gfx9_modifiers()458 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in amdgpu_dm_plane_add_gfx9_modifiers()459 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in amdgpu_dm_plane_add_gfx9_modifiers()[all …]
758 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in convert_tiling_flags_to_modifier()759 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; in convert_tiling_flags_to_modifier()837 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); in convert_tiling_flags_to_modifier()842 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()848 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()849 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()851 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()853 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
927 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_4_3_gpu_early_init()934 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_4_3_gpu_early_init()936 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_4_3_gpu_early_init()941 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_4_3_gpu_early_init()946 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_4_3_gpu_early_init()951 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_4_3_gpu_early_init()956 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_4_3_gpu_early_init()
223 struct gb_addr_config gb_addr_config_fields; member
3450 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()3455 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()3460 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()3462 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()3465 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()3468 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()3471 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
4584 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()4589 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()4594 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()4596 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()4599 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()4602 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()4605 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
2114 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()2121 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()2123 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()2128 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()2133 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()2138 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()2143 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
4607 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()4626 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()4631 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()4633 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()4636 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()4639 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()4642 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()