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Searched refs:gb_addr_config (Results 1 – 25 of 51) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c391 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
393 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
395 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
397 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
399 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
401 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
403 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
405 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
407 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
409 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
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H A Dgfx_v6_0.c1578 u32 gb_addr_config = 0; in gfx_v6_0_constants_init() local
1600 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1617 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1634 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1651 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1668 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1710 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v6_0_constants_init()
1712 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); in gfx_v6_0_constants_init()
1713 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); in gfx_v6_0_constants_init()
1714 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); in gfx_v6_0_constants_init()
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H A Djpeg_v5_0_0.c362 adev->gfx.config.gb_addr_config, indirect); in jpeg_v5_0_0_start_dpg_mode()
365 adev->gfx.config.gb_addr_config, 1); in jpeg_v5_0_0_start_dpg_mode()
448 adev->gfx.config.gb_addr_config); in jpeg_v5_0_0_start()
H A Duvd_v3_1.c270 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
271 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
272 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
H A Duvd_v4_2.c604 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
605 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
606 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
H A Damdgpu_gfx.h180 struct gb_addr_config { struct
215 unsigned gb_addr_config; member
223 struct gb_addr_config gb_addr_config_fields;
H A Duvd_v5_0.c307 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
308 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
309 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
H A Djpeg_v3_0.c366 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
368 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
H A Dsoc24.c162 adev->gfx.config.gb_addr_config) in soc24_get_register_value()
163 return adev->gfx.config.gb_addr_config; in soc24_get_register_value()
H A Dgfx_v9_0.c2023 u32 gb_addr_config; in gfx_v9_0_gpu_early_init() local
2052 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
2053 gb_addr_config |= 0x22014042; in gfx_v9_0_gpu_early_init()
2079 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
2080 gb_addr_config |= 0x22014042; in gfx_v9_0_gpu_early_init()
2089 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
2090 gb_addr_config |= 0x22010042; in gfx_v9_0_gpu_early_init()
2100 gb_addr_config &= ~0xf3e777ff; in gfx_v9_0_gpu_early_init()
2101 gb_addr_config |= 0x22014042; in gfx_v9_0_gpu_early_init()
2112 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
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H A Dgfx_v7_0.c1896 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1897 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
1898 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v7_0_constants_init()
4178 u32 gb_addr_config; in gfx_v7_0_gpu_early_init() local
4199 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4216 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4233 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4252 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in gfx_v7_0_gpu_early_init()
4304 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v7_0_gpu_early_init()
4308 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); in gfx_v7_0_gpu_early_init()
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H A Dgfx_v8_0.c1667 u32 gb_addr_config; in gfx_v8_0_gpu_early_init() local
1689 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1706 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1736 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1753 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1770 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1804 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; in gfx_v8_0_gpu_early_init()
1859 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); in gfx_v8_0_gpu_early_init()
1862 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); in gfx_v8_0_gpu_early_init()
1865 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); in gfx_v8_0_gpu_early_init()
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H A Djpeg_v2_5.c350 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start_inst()
352 adev->gfx.config.gb_addr_config); in jpeg_v2_5_start_inst()
H A Djpeg_v4_0_5.c451 adev->gfx.config.gb_addr_config, indirect); in jpeg_v4_0_5_start_dpg_mode()
536 adev->gfx.config.gb_addr_config); in jpeg_v4_0_5_start()
H A Dsoc21.c296 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
297 return adev->gfx.config.gb_addr_config; in soc21_get_register_value()
H A Duvd_v6_0.c631 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
632 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
633 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
H A Dvcn_v4_0_3.c620 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
622 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1242 adev->gfx.config.gb_addr_config); in vcn_v4_0_3_start()
1244 adev->gfx.config.gb_addr_config); in vcn_v4_0_3_start()
H A Dgfx_v12_0.c3444 u32 gb_addr_config; in get_gb_addr_config() local
3446 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
3447 if (gb_addr_config == 0) in get_gb_addr_config()
3451 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); in get_gb_addr_config()
3453 adev->gfx.config.gb_addr_config = gb_addr_config; in get_gb_addr_config()
3456 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
3463 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
3466 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
3469 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
3472 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in get_gb_addr_config()
H A Duvd_v7_0.c720 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
722 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
724 adev->gfx.config.gb_addr_config); in uvd_v7_0_mc_resume()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dni.c867 u32 gb_addr_config = 0; in cayman_gpu_init() local
900 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
974 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1101 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1102 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1104 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cayman_gpu_init()
1105 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1108 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1109 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1110 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
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H A Devergreen.c3134 u32 gb_addr_config; in evergreen_gpu_init() local
3242 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3264 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3292 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; in evergreen_gpu_init()
3449 ((gb_addr_config & 0x30000000) >> 28) << 12; in evergreen_gpu_init()
3497 WREG32(GB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3498 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3499 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3500 WREG32(DMA_TILING_CONFIG, gb_addr_config); in evergreen_gpu_init()
3501 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
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H A Dsi.c3071 u32 gb_addr_config = 0; in si_gpu_init() local
3129 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3146 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3199 gb_addr_config &= ~ROW_SIZE_MASK; in si_gpu_init()
3203 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3206 gb_addr_config |= ROW_SIZE(1); in si_gpu_init()
3209 gb_addr_config |= ROW_SIZE(2); in si_gpu_init()
3254 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3255 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3256 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
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H A Dcik.c3170 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init() local
3192 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3209 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; in cik_gpu_init()
3279 gb_addr_config &= ~ROW_SIZE_MASK; in cik_gpu_init()
3283 gb_addr_config |= ROW_SIZE(0); in cik_gpu_init()
3286 gb_addr_config |= ROW_SIZE(1); in cik_gpu_init()
3289 gb_addr_config |= ROW_SIZE(2); in cik_gpu_init()
3324 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3325 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3326 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
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/linux-6.15/drivers/gpu/drm/amd/include/
H A Dkgd_kfd_interface.h155 uint32_t gb_addr_config; member
/linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c636 u32 gb_addr_config; in amdgpu_dm_plane_add_gfx11_modifiers() local
646 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in amdgpu_dm_plane_add_gfx11_modifiers()
647 ASSERT(gb_addr_config != 0); in amdgpu_dm_plane_add_gfx11_modifiers()
649 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); in amdgpu_dm_plane_add_gfx11_modifiers()
651 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); in amdgpu_dm_plane_add_gfx11_modifiers()

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