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Searched refs:fuses (Results 1 – 25 of 30) sorted by relevance

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/linux-6.15/drivers/thermal/renesas/
H A Drcar_gen3_thermal.c264 const struct rcar_gen3_thermal_fuse_info *fuses = priv->info->fuses; in rcar_gen3_thermal_fetch_fuses() local
272 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
274 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
276 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
282 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
284 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
286 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
297 if (!priv->info->fuses || in rcar_gen3_thermal_read_fuses()
368 .fuses = &rcar_gen3_thermal_fuse_info_gen3,
375 .fuses = &rcar_gen3_thermal_fuse_info_gen3,
[all …]
/linux-6.15/drivers/nvmem/
H A Dapple-efuses.c15 void __iomem *fuses; member
25 *dst++ = readl_relaxed(priv->fuses + offset); in apple_efuses_read()
53 priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in apple_efuses_probe()
54 if (IS_ERR(priv->fuses)) in apple_efuses_probe()
55 return PTR_ERR(priv->fuses); in apple_efuses_probe()
H A DKconfig254 Enable support for reading the fuses in the E-FUSE or OTP
/linux-6.15/drivers/crypto/intel/qat/qat_c62x/
H A Dadf_c62x_hw_data.c30 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
34 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET; in get_accel_mask()
42 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
54 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK; in get_ae_mask()
H A Dadf_drv.c129 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
172 i = (hw_data->fuses[ADF_FUSECTL0] & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; in adf_probe()
/linux-6.15/drivers/crypto/intel/qat/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c30 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
34 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET; in get_accel_mask()
42 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
54 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK; in get_ae_mask()
H A Dadf_drv.c129 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
/linux-6.15/drivers/crypto/intel/qat/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c32 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
34 return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & in get_accel_mask()
40 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
42 return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK; in get_ae_mask()
102 int sku = (self->fuses[ADF_FUSECTL0] & ADF_DH895XCC_FUSECTL_SKU_MASK) in get_sku()
H A Dadf_drv.c129 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
/linux-6.15/drivers/pmdomain/qcom/
H A Dcpr.c804 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx() local
808 for (; fuse < end; fuse++, fuses++) { in cpr_populate_ring_osc_idx()
846 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init() local
1166 quot_offset = fuses[fnum].quotient_offset; in cpr_corner_init()
1219 struct cpr_fuse *fuses; in cpr_get_fuses() local
1225 if (!fuses) in cpr_get_fuses()
1233 if (!fuses[i].ring_osc) in cpr_get_fuses()
1239 if (!fuses[i].init_voltage) in cpr_get_fuses()
1244 if (!fuses[i].quotient) in cpr_get_fuses()
1250 if (!fuses[i].quotient_offset) in cpr_get_fuses()
[all …]
/linux-6.15/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen2_hw_data.c118 u32 fuses = hw_data->fuses[ADF_FUSECTL0]; in adf_gen2_get_accel_cap() local
144 if ((straps | fuses) & ADF_POWERGATE_PKE) in adf_gen2_get_accel_cap()
147 if ((straps | fuses) & ADF_POWERGATE_DC) in adf_gen2_get_accel_cap()
H A Dadf_accel_devices.h358 u32 fuses[ADF_MAX_FUSES]; member
/linux-6.15/Documentation/devicetree/bindings/cpufreq/
H A Dimx-cpufreq-dt.txt5 "speed grading" value which are written in fuses. These bits are combined with
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml167 nvidia,xcvr-setup-use-fuses:
168 description: Indicates that the value is read from the on-chip fuses.
254 - required: ["nvidia,xcvr-setup-use-fuses"]
/linux-6.15/Documentation/devicetree/bindings/iio/adc/
H A Dmicrochip,mcp3564.yaml84 The address is set on a per-device basis by fuses in the factory,
85 configured on request. If not requested, the fuses are set for 0x1.
/linux-6.15/drivers/crypto/intel/qat/qat_420xx/
H A Dadf_drv.c82 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]); in adf_probe()
H A Dadf_420xx_hw_data.c101 u32 me_disable = self->fuses[ADF_FUSECTL4]; in get_ae_mask()
/linux-6.15/drivers/crypto/intel/qat/qat_4xxx/
H A Dadf_drv.c84 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]); in adf_probe()
H A Dadf_4xxx_hw_data.c104 u32 me_disable = self->fuses[ADF_FUSECTL4]; in get_ae_mask()
/linux-6.15/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts590 /delete-property/ nvidia,xcvr-setup-use-fuses;
595 /delete-property/ nvidia,xcvr-setup-use-fuses;
H A Dtegra30.dtsi1143 nvidia,xcvr-setup-use-fuses;
1186 nvidia,xcvr-setup-use-fuses;
1228 nvidia,xcvr-setup-use-fuses;
H A Dtegra20-asus-tf101.dts880 nvidia,xcvr-setup-use-fuses;
893 nvidia,xcvr-setup-use-fuses;
H A Dtegra20-acer-a500-picasso.dts1107 nvidia,xcvr-setup-use-fuses;
1118 nvidia,xcvr-setup-use-fuses;
/linux-6.15/drivers/nvme/target/
H A Dpassthru.c138 id->fuses = 0; in nvmet_passthru_override_id_ctrl()
/linux-6.15/Documentation/security/keys/
H A Dtrusted-encrypted.rst36 fuses and is accessible to TEE only.
48 in the on-chip fuses and is accessible to the DCP encryption engine only.

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