Home
last modified time | relevance | path

Searched refs:duty (Results 1 – 25 of 148) sorted by relevance

123456

/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dfanpwm.c44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
74 duty = ((divs * percent) + 99) / 100; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
78 ret = therm->func->pwm_set(therm, fan->func.line, divs, duty); in nvkm_fanpwm_set()
91 u32 divs, duty; in nvkm_fanpwm_create() local
[all …]
H A Dfan.c39 int duty; in nvkm_fan_update() local
53 duty = fan->get(therm); in nvkm_fan_update()
54 if (duty == target) { in nvkm_fan_update()
65 if (duty < target) in nvkm_fan_update()
66 duty = min(duty + 3, target); in nvkm_fan_update()
67 else if (duty > target) in nvkm_fan_update()
68 duty = max(duty - 3, target); in nvkm_fan_update()
70 duty = target; in nvkm_fan_update()
86 if (target != duty) { in nvkm_fan_update()
91 if (duty > target) in nvkm_fan_update()
[all …]
H A Dbase.c44 u16 duty, i; in nvkm_therm_update_trip() local
59 duty = cur_trip->fan_duty; in nvkm_therm_update_trip()
62 duty = 0; in nvkm_therm_update_trip()
66 return duty; in nvkm_therm_update_trip()
74 u16 duty; in nvkm_therm_compute_linear_duty() local
87 return duty; in nvkm_therm_compute_linear_duty()
113 int duty = -1; in nvkm_therm_update() local
124 if (duty < 0) in nvkm_therm_update()
125 duty = 100; in nvkm_therm_update()
138 duty = therm->cstate; in nvkm_therm_update()
[all …]
H A Dgf119.c68 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
77 *duty = nvkm_rd32(device, 0x00e118 + (indx * 8)); in gf119_fan_pwm_get()
82 *duty = nvkm_rd32(device, 0x0200dc) & 0x1fff; in gf119_fan_pwm_get()
90 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
98 nvkm_wr32(device, 0x00e118 + (indx * 8), duty | 0x80000000); in gf119_fan_pwm_set()
101 nvkm_wr32(device, 0x0200dc, duty | 0x40000000); in gf119_fan_pwm_set()
H A Dgm107.c34 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
38 *duty = nvkm_rd32(device, 0x10eb24) & 0x1fff; in gm107_fan_pwm_get()
43 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
47 nvkm_wr32(device, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
H A Dfantog.c46 int duty; in nvkm_fantog_update() local
53 duty = !nvkm_gpio_get(gpio, 0, DCB_GPIO_FAN, 0xff); in nvkm_fantog_update()
54 nvkm_gpio_set(gpio, 0, DCB_GPIO_FAN, 0xff, duty); in nvkm_fantog_update()
56 if (percent != (duty * 100)) { in nvkm_fantog_update()
58 if (!duty) in nvkm_fantog_update()
H A Dnv40.c121 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv40_fan_pwm_get() argument
128 *duty = (reg & 0x7fff0000) >> 16; in nv40_fan_pwm_get()
137 *duty = (reg & 0x7fffffff); in nv40_fan_pwm_get()
149 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv40_fan_pwm_set() argument
154 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
158 nvkm_mask(device, 0x0015f4, 0x7fffffff, duty); in nv40_fan_pwm_set()
/linux-6.15/drivers/pwm/
H A Dpwm-ntxec.c57 int period, int duty) in ntxec_pwm_set_raw_period_and_duty_cycle() argument
74 { NTXEC_REG_DUTY_HIGH, ntxec_reg8(duty >> 8) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
76 { NTXEC_REG_DUTY_LOW, ntxec_reg8(duty) }, in ntxec_pwm_set_raw_period_and_duty_cycle()
86 unsigned int period, duty; in ntxec_pwm_apply() local
93 duty = min_t(u64, state->duty_cycle, period); in ntxec_pwm_apply()
96 duty /= TIME_BASE_NS; in ntxec_pwm_apply()
107 if (state->enabled && duty != 0) { in ntxec_pwm_apply()
108 res = ntxec_pwm_set_raw_period_and_duty_cycle(chip, period, duty); in ntxec_pwm_apply()
H A Dpwm-renesas-tpu.c77 u16 duty; member
181 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); in tpu_pwm_timer_start()
185 tpd->channel, tpd->duty, tpd->period); in tpu_pwm_timer_start()
227 tpd->duty = 0; in tpu_pwm_request()
251 u32 duty; in tpu_pwm_config() local
306 duty = 0; in tpu_pwm_config()
317 tpd->duty = duty; in tpu_pwm_config()
331 tpd->duty); in tpu_pwm_config()
339 if (duty == 0 || duty == period) { in tpu_pwm_config()
376 if (tpd->duty == 0 || tpd->duty == tpd->period) { in tpu_pwm_enable()
[all …]
H A Dpwm-sunplus.c59 u32 dd_freq, duty, mode0, mode1; in sunplus_pwm_apply() local
110 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
118 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
120 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
131 u32 mode0, dd_freq, duty; in sunplus_pwm_get_state() local
139 duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_get_state()
140 duty = FIELD_GET(SP7021_PWM_DUTY_MASK, duty); in sunplus_pwm_get_state()
150 state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC, in sunplus_pwm_get_state()
H A Dpwm-atmel-tcb.c80 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
95 &tcbpwm->duty); in atmel_tcb_pwm_request()
99 &tcbpwm->duty); in atmel_tcb_pwm_request()
137 if (tcbpwm->duty == 0) in atmel_tcb_pwm_disable()
191 if (tcbpwm->duty == 0) in atmel_tcb_pwm_enable()
221 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) { in atmel_tcb_pwm_enable()
242 tcbpwm->duty); in atmel_tcb_pwm_enable()
246 tcbpwm->duty); in atmel_tcb_pwm_enable()
268 unsigned duty; in atmel_tcb_pwm_config() local
317 if ((atcbpwm->duty > 0 && atcbpwm->duty != atcbpwm->period) && in atmel_tcb_pwm_config()
[all …]
H A Dpwm-dwc-core.c124 u64 duty, period; in dwc_pwm_get_state() local
140 duty = (ld + 1) * dwc->clk_ns; in dwc_pwm_get_state()
142 period += duty; in dwc_pwm_get_state()
144 duty = (ld + 1) * dwc->clk_ns; in dwc_pwm_get_state()
145 period = duty * 2; in dwc_pwm_get_state()
150 state->duty_cycle = duty; in dwc_pwm_get_state()
H A Dpwm-rockchip.c40 unsigned long duty; member
84 tmp = readl_relaxed(pc->base + pc->data->regs.duty); in rockchip_pwm_get_state()
106 unsigned long period, duty; in rockchip_pwm_config() local
122 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
135 writel(duty, pc->base + pc->data->regs.duty); in rockchip_pwm_config()
234 .duty = 0x04,
247 .duty = 0x08,
261 .duty = 0x08,
275 .duty = 0x08,
H A Dpwm-pca9685.c135 static void pca9685_pwm_set_duty(struct pwm_chip *chip, int channel, unsigned int duty) in pca9685_pwm_set_duty() argument
140 if (duty == 0) { in pca9685_pwm_set_duty()
144 } else if (duty >= PCA9685_COUNTER_RANGE) { in pca9685_pwm_set_duty()
164 off = (on + duty) % PCA9685_COUNTER_RANGE; in pca9685_pwm_set_duty()
371 unsigned long long duty, prescale; in __pca9685_pwm_apply() local
413 duty = PCA9685_COUNTER_RANGE * state->duty_cycle; in __pca9685_pwm_apply()
414 duty = DIV_ROUND_UP_ULL(duty, state->period); in __pca9685_pwm_apply()
415 pca9685_pwm_set_duty(chip, pwm->hwpwm, duty); in __pca9685_pwm_apply()
441 unsigned long long duty; in pca9685_pwm_get_state() local
468 duty = pca9685_pwm_get_duty(chip, pwm->hwpwm); in pca9685_pwm_get_state()
[all …]
/linux-6.15/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c42 u32 div, duty; in nouveau_led_get_brightness() local
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
48 return duty * LED_FULL / div; in nouveau_led_get_brightness()
62 u32 div, duty; in nouveau_led_set_brightness() local
65 duty = value * div / LED_FULL; in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk104.c43 u32 div, duty; in gk104_volt_get() local
46 duty = nvkm_rd32(device, 0x20344); in gk104_volt_get()
48 return bios->base + bios->pwm_range * duty / div; in gk104_volt_get()
56 u32 div, duty; in gk104_volt_set() local
60 duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range); in gk104_volt_set()
63 nvkm_wr32(device, 0x20344, 0x80000000 | duty); in gk104_volt_set()
/linux-6.15/Documentation/hwmon/
H A Dnzxt-kraken3.rst26 Kraken 2023 models additionally expose the speed and duty of an optionally connected
29 Pump and fan duty control mode can be set through pwm[1-2]_enable, where 1 is
32 duty to 100%.
62 2 Curve control mode (applies the temp-PWM duty curve based on coolant temp)
72 pwm1 Pump duty (value between 0-255)
73 pwm1_enable Pump duty control mode (0: disabled, 1: manual, 2: curve)
74 pwm2 Fan duty (value between 0-255)
75 pwm2_enable Fan duty control mode (0: disabled, 1: manual, 2: curve)
76 temp[1-2]_auto_point[1-40]_pwm Temp-PWM duty curves (for pump and fan), related to coolant temp
H A Ddme1737.rst199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
215 all PWM outputs are set to 100% duty-cycle.
228 duty-cycle >
288 to full-speed (100% duty-cycle).
299 fan[5-6]_max RW Max attainable RPM at 100% duty-cycle.
320 fast the PWM duty-cycle will change
324 (default is 0, which means the duty-
339 low-speed duty-cycle.
341 full-speed duty-cycle which is hard-
[all …]
H A Dvt1211.rst181 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
186 thermal thresholds exist that controls both PWMs output duty-cycles. The
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
218 - full speed duty-cycle full speed duty-cycle
220 - high speed duty-cycle full speed duty-cycle
222 - low speed duty-cycle high speed duty-cycle
[all …]
/linux-6.15/drivers/clk/meson/
H A Dsclk-div.c126 struct clk_duty *duty) in sclk_div_set_duty_cycle() argument
132 memcpy(&sclk->cached_duty, duty, sizeof(*duty)); in sclk_div_set_duty_cycle()
140 struct clk_duty *duty) in sclk_div_get_duty_cycle() argument
147 duty->num = 1; in sclk_div_get_duty_cycle()
148 duty->den = 2; in sclk_div_get_duty_cycle()
153 duty->num = hi + 1; in sclk_div_get_duty_cycle()
154 duty->den = sclk->cached_div; in sclk_div_get_duty_cycle()
/linux-6.15/Documentation/devicetree/bindings/input/
H A Dpwm-vibrator.yaml14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
58 direction-duty-cycle-ns = <1000000000>;
/linux-6.15/drivers/leds/rgb/
H A Dleds-pwm-multicolor.c36 unsigned long long duty; in led_pwm_mc_set() local
45 duty = priv->leds[i].state.period; in led_pwm_mc_set()
46 duty *= mc_cdev->subled_info[i].brightness; in led_pwm_mc_set()
47 do_div(duty, cdev->max_brightness); in led_pwm_mc_set()
50 duty = priv->leds[i].state.period - duty; in led_pwm_mc_set()
52 priv->leds[i].state.duty_cycle = duty; in led_pwm_mc_set()
/linux-6.15/include/trace/events/
H A Dclk.h233 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
235 TP_ARGS(core, duty),
245 __entry->num = duty->num;
246 __entry->den = duty->den;
255 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
257 TP_ARGS(core, duty)
262 TP_PROTO(struct clk_core *core, struct clk_duty *duty),
264 TP_ARGS(core, duty)
/linux-6.15/drivers/leds/
H A Dleds-pwm.c46 unsigned long long duty = led_dat->pwmstate.period; in led_pwm_set() local
48 duty *= brightness; in led_pwm_set()
49 do_div(duty, max); in led_pwm_set()
52 duty = led_dat->pwmstate.period - duty; in led_pwm_set()
54 led_dat->pwmstate.duty_cycle = duty; in led_pwm_set()
/linux-6.15/Documentation/devicetree/bindings/regulator/
H A Dpwm-regulator.yaml19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
104 * Inverted PWM logic, and the duty cycle range is limited

123456