Searched refs:dtbclk (Results 1 – 11 of 11) sorted by relevance
432 int dtbclk; in dcn35_smu_get_dtbclk() local437 dtbclk = dcn35_smu_send_msg_with_param(clk_mgr, in dcn35_smu_get_dtbclk()441 smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); in dcn35_smu_get_dtbclk()442 return dtbclk * 1000; in dcn35_smu_get_dtbclk()
182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()
215 dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; in dml21_apply_soc_bb_overrides()217 if (i < dml_clk_table->dtbclk.num_clk_values) { in dml21_apply_soc_bb_overrides()221 dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; in dml21_apply_soc_bb_overrides()222 dml_clk_table->dtbclk.num_clk_values = i + 1; in dml21_apply_soc_bb_overrides()224 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()225 dml_clk_table->dtbclk.num_clk_values = i; in dml21_apply_soc_bb_overrides()228 dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; in dml21_apply_soc_bb_overrides()231 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in dml21_apply_soc_bb_overrides()
121 struct dml2_clk_table dtbclk; member
106 .dtbclk = {
179 uint32_t dtbclk; member
375 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()502 clk_register_dump.dtbclk, in dcn401_auto_dpm_test_log()1471 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk; in dcn401_get_dtb_ref_freq_khz()1552 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn401_clk_mgr_construct()1553 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn401_clk_mgr_construct()
934 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct()1200 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn32_clk_mgr_construct()
34 unsigned int dtbclk; member
404 …dtbclk_khz, &display_cfg->stream_programming[i].min_clocks.dcn4x.dtbclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm()413 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dtbrefclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm()
8141 if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_clocks_khz.dtbclk / 1000)) { in dml_core_mode_support()