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Searched refs:dscclk_mhz (Results 1 – 20 of 20) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c129 .dscclk_mhz = 186.0,
138 .dscclk_mhz = 209.0,
147 .dscclk_mhz = 209.0,
156 .dscclk_mhz = 371.0,
165 .dscclk_mhz = 417.0,
373 .dscclk_mhz = 186.0,
382 .dscclk_mhz = 209.0,
391 .dscclk_mhz = 209.0,
400 .dscclk_mhz = 371.0,
644 s[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c109 .dscclk_mhz = 200.0,
122 .dscclk_mhz = 266.7,
135 .dscclk_mhz = 266.7,
148 .dscclk_mhz = 320.0,
161 .dscclk_mhz = 355.6,
174 .dscclk_mhz = 400.0,
187 .dscclk_mhz = 457.1,
200 .dscclk_mhz = 533.3,
337 clock_limits[i].dscclk_mhz = in dcn351_update_bw_bounding_box_fpu()
338 dcn3_51_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn351_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c110 .dscclk_mhz = 186.0,
119 .dscclk_mhz = 209.0,
128 .dscclk_mhz = 209.0,
137 .dscclk_mhz = 371.0,
146 .dscclk_mhz = 417.0,
251 clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn314_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c120 .dscclk_mhz = 206.0,
132 .dscclk_mhz = 206.0,
144 .dscclk_mhz = 296.0,
156 .dscclk_mhz = 338.0,
168 .dscclk_mhz = 338.0,
360 s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn301_fpu_update_bw_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c232 .dscclk_mhz = 171.0,
243 .dscclk_mhz = 214.0,
254 .dscclk_mhz = 245.0,
265 .dscclk_mhz = 367.0,
454 .dscclk_mhz = 171.0,
465 .dscclk_mhz = 214.0,
476 .dscclk_mhz = 245.0,
487 .dscclk_mhz = 367.0,
498 .dscclk_mhz = 428.0,
509 .dscclk_mhz = 428.0,
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c126 .dscclk_mhz = 186.0,
135 .dscclk_mhz = 209.0,
144 .dscclk_mhz = 209.0,
153 .dscclk_mhz = 371.0,
162 .dscclk_mhz = 400.0,
303 clock_limits[i].dscclk_mhz = in dcn35_update_bw_bounding_box_fpu()
304 dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn35_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c121 .dscclk_mhz = 405.6,
340 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; in dcn302_fpu_update_bw_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c120 .dscclk_mhz = 405.6,
346 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; in dcn303_fpu_update_bw_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h28 uint32_t dscclk_mhz; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c142 .dscclk_mhz = 400.0,
153 .dscclk_mhz = 400.0,
164 .dscclk_mhz = 400.0,
175 .dscclk_mhz = 400.0,
187 .dscclk_mhz = 400.0,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c133 .dscclk_mhz = 405.6,
595 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; in dcn30_fpu_update_bw_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c117 .dscclk_mhz = 573.333,
426 entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3; in build_synthetic_soc_states()
826 dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; in dcn321_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c360 p->in_states->state_array[0].dscclk_mhz = 716.667; in dml2_init_soc_states()
396 p->in_states->state_array[0].dscclk_mhz = 573.333; in dml2_init_soc_states()
431 p->in_states->state_array[0].dscclk_mhz = 666.667; //716.667; in dml2_init_soc_states()
593 p->out_states->state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0; in dml2_init_soc_states()
726 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
H A Ddml2_policy.c172 s->entry.dscclk_mhz = max_dispclk_mhz / 3; in dml2_policy_build_synthetic_soc_states()
H A Ddisplay_mode_util.c624 dml_print("DML: state_bbox: dscclk_mhz = %f\n", state->dscclk_mhz); in dml_print_soc_state_bounding_box()
H A Ddisplay_mode_core_structs.h280 dml_float_t dscclk_mhz; member
H A Ddisplay_mode_core.c7416 …Factor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) { in dml_core_mode_support()
7419 …_print("DML::%s: k=%u, DSCCLKPerState = %f\n", __func__, k, mode_lib->ms.state.dscclk_mhz); in dml_core_mode_support()
7425 …Factor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) { in dml_core_mode_support()
7429 …Factor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) { in dml_core_mode_support()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h158 double dscclk_mhz; member
H A Ddisplay_mode_vba.c402 mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz; in fetch_socbb_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c138 .dscclk_mhz = 716.667,
2879 entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3; in build_synthetic_soc_states()
3271 dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; in dcn32_update_bw_bounding_box_fpu()