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Searched refs:dsc_dpcd (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/include/drm/display/
H A Ddrm_dp_helper.h200 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
201 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
203 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
208 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_sink_supports_dsc()
210 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & in drm_dp_sink_supports_dsc()
215 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_edp_dsc_sink_output_bpp()
217 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | in drm_edp_dsc_sink_output_bpp()
218 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & in drm_edp_dsc_sink_output_bpp()
223 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_max_slice_width()
226 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * in drm_dp_dsc_sink_max_slice_width()
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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp.c1405 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) in intel_dp_has_dsc()
1485 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_mode_valid()
1896 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
2104 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); in intel_dp_dsc_bpp_step_x16()
2390 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, in intel_dp_dsc_compute_config()
4030 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in intel_dp_read_dsc_dpcd()
4032 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, in intel_dp_read_dsc_dpcd()
4042 dsc_dpcd); in intel_dp_read_dsc_dpcd()
4053 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); in intel_dp_get_dsc_sink_cap()
4062 connector->dp.dsc_dpcd); in intel_dp_get_dsc_sink_cap()
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H A Dintel_display_debugfs.c939 str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))); in i915_dsc_fec_support_show()
941 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
943 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
945 str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, in i915_dsc_fec_support_show()
948 drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd)); in i915_dsc_fec_support_show()
950 drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp))); in i915_dsc_fec_support_show()
H A Dintel_display_types.h541 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; member
H A Dintel_dp_mst.c436 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, in mst_stream_dsc_compute_link_config()
/linux-6.15/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c2601 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_bpp_incr()
2603 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2638 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_max_slice_count()
2641 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2653 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2696 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_line_buf_depth()
2698 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2742 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_supported_input_bpcs()
2746 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()
2748 if (!drm_dp_sink_supports_dsc(dsc_dpcd)) in drm_dp_dsc_sink_supported_input_bpcs()