Searched refs:drr_config (Results 1 – 8 of 8) sorted by relevance
968 if (master_timing->drr_config.enabled) { in build_synchronized_timing_groups()971 (master_timing->drr_config.drr_active_fixed || master_timing->drr_config.drr_active_variable); in build_synchronized_timing_groups()1051 if (!stream_descriptor->timing.drr_config.enabled) in all_timings_support_drr()1526 stream_descriptor->timing.drr_config.enabled && in stream_matches_drr_policy()1527 …(stream_descriptor->timing.drr_config.drr_active_fixed || stream_descriptor->timing.drr_config.drr… in stream_matches_drr_policy()1532 stream_descriptor->timing.drr_config.enabled && in stream_matches_drr_policy()1538 stream_descriptor->timing.drr_config.enabled && in stream_matches_drr_policy()1544 !stream_descriptor->timing.drr_config.enabled || in stream_matches_drr_policy()1550 (!stream_descriptor->timing.drr_config.enabled || in stream_matches_drr_policy()1551 …(!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.d… in stream_matches_drr_policy()[all …]
225 if (display_config->display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()
381 timing->drr_config.enabled = stream->ignore_msa_timing_param; in populate_dml21_timing_config_from_stream_state()382 timing->drr_config.drr_active_variable = stream->vrr_active_variable; in populate_dml21_timing_config_from_stream_state()383 timing->drr_config.drr_active_fixed = stream->vrr_active_fixed; in populate_dml21_timing_config_from_stream_state()384 timing->drr_config.disallowed = !stream->allow_freesync; in populate_dml21_timing_config_from_stream_state()394 timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz; in populate_dml21_timing_config_from_stream_state()396 timing->drr_config.min_refresh_uhz = min_hardware_refresh_in_uhz; in populate_dml21_timing_config_from_stream_state()401 …timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instan… in populate_dml21_timing_config_from_stream_state()403 timing->drr_config.max_instant_vtotal_delta = 0; in populate_dml21_timing_config_from_stream_state()
273 } drr_config; member
584 phantom->timing.drr_config.enabled = false; in create_phantom_stream_from_main_stream()
165 phantom->timing.drr_config.enabled = false; in create_phantom_stream_from_main_stream()
9000 …cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? in dml_core_mode_support()11232 …cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? in dml_core_mode_programming()12829 base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled; in dml2_core_calcs_get_stream_fams2_programming()
447 if (display_config->stream_descriptors[remap_array[i]].timing.drr_config.enabled) { in are_timings_trivially_synchronizable()