Home
last modified time | relevance | path

Searched refs:dram_clock_change_latency_us (Results 1 – 25 of 28) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c205 .dram_clock_change_latency_us = 23.84,
299 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
319 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
380 if ((int)(dcn3_01_soc.dram_clock_change_latency_us * 1000) in dcn301_fpu_update_bw_bounding_box()
383 dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0; in dcn301_fpu_update_bw_bounding_box()
403 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn301_fpu_init_soc_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
659 if ((int)(dcn3_1_soc.dram_clock_change_latency_us * 1000) in dcn31_update_bw_bounding_box()
662 dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn31_update_bw_bounding_box()
720 if ((int)(dcn3_15_soc.dram_clock_change_latency_us * 1000) in dcn315_update_bw_bounding_box()
723 dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn315_update_bw_bounding_box()
800 if ((int)(dcn3_16_soc.dram_clock_change_latency_us * 1000) in dcn316_update_bw_bounding_box()
803 dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn316_update_bw_bounding_box()
821 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp in dcn_get_approx_det_segs_required_for_pstate()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c167 .dram_clock_change_latency_us = 404,
296 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
297 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
341 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
365 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
411 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
432 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
514 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
631 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
659 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_fpu_build_wm_range_table()
[all …]
H A Ddisplay_rq_dlg_calc_30.c1237 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c180 .dram_clock_change_latency_us = 34.0,
323 if ((int)(dcn3_5_soc.dram_clock_change_latency_us * 1000) in dcn35_update_bw_bounding_box_fpu()
326 dcn3_5_soc.dram_clock_change_latency_us = in dcn35_update_bw_bounding_box_fpu()
331 dcn3_5_soc.dram_clock_change_latency_us = in dcn35_update_bw_bounding_box_fpu()
392 …dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latenc… in dcn35_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c218 .dram_clock_change_latency_us = 34,
357 if ((int)(dcn3_51_soc.dram_clock_change_latency_us * 1000) in dcn351_update_bw_bounding_box_fpu()
360 dcn3_51_soc.dram_clock_change_latency_us = in dcn351_update_bw_bounding_box_fpu()
365 dcn3_51_soc.dram_clock_change_latency_us = in dcn351_update_bw_bounding_box_fpu()
425 …dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_51_soc.dram_clock_change_laten… in dcn351_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h71 uint32_t dram_clock_change_latency_us; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
132 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn401_update_bw_bounding_box_fpu()
144 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn401_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c155 .dram_clock_change_latency_us = 400,
638 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) in dcn321_update_bw_bounding_box_fpu()
641 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
642 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
667 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
668 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn10/
H A Ddcn10_fpu.c122 .dram_clock_change_latency_us = 17.0,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c155 .dram_clock_change_latency_us = 404,
355 dcn3_02_soc.dram_clock_change_latency_us = in dcn302_fpu_init_soc_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c154 .dram_clock_change_latency_us = 404,
373 dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn303_fpu_init_soc_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c323 .dram_clock_change_latency_us = 404.0,
434 .dram_clock_change_latency_us = 404.0,
545 .dram_clock_change_latency_us = 45.0,
759 .dram_clock_change_latency_us = 23.84,
2014 if ((int)(bb->dram_clock_change_latency_us * 1000) in dcn20_patch_bounding_box()
2017 bb->dram_clock_change_latency_us = in dcn20_patch_bounding_box()
2089 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; in dcn20_validate_bandwidth_fp()
2128 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; in dcn20_validate_bandwidth_fp()
2214 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
2222 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
[all …]
H A Ddisplay_rq_dlg_calc_20.c1083 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
H A Ddisplay_rq_dlg_calc_20v2.c1084 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c379 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
415 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
450 p->in_states->state_array[0].dram_clock_change_latency_us = 400; in dml2_init_soc_states()
491 if (dml2->config.bbox_overrides.dram_clock_change_latency_us) { in dml2_init_soc_states()
492 p->in_states->state_array[i].dram_clock_change_latency_us = in dml2_init_soc_states()
493 dml2->config.bbox_overrides.dram_clock_change_latency_us; in dml2_init_soc_states()
733 out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us; in dml2_translate_soc_states()
H A Ddml2_wrapper.h192 double dram_clock_change_latency_us; member
H A Ddml2_wrapper.c263 …lk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us; in calculate_lowest_supported_state_for_temp_read()
268 …dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate… in calculate_lowest_supported_state_for_temp_read()
292 …dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latenci… in calculate_lowest_supported_state_for_temp_read()
H A Ddisplay_mode_util.c644 …print("DML: state_bbox: dram_clock_change_latency_us = %f\n", state->dram_clock_change_latency_us); in dml_print_soc_state_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c176 .dram_clock_change_latency_us = 400,
291 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
2343 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2381 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2507 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2528 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2620 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
3075 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) in dcn32_update_bw_bounding_box_fpu()
3078 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
3079 dcn3_2_soc.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h235 double dram_clock_change_latency_us; member
H A Ddml1_display_rq_dlg_calc.c1307 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()
1323 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
H A Ddisplay_mode_vba.c358 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()
359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c228 .dram_clock_change_latency_us = 250.0,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c1131 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()

12