Searched refs:dpu_hw_blk (Results 1 – 15 of 15) sorted by relevance
29 struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];30 struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];31 struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];34 struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];35 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];36 struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];37 struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];39 struct dpu_hw_blk *cdm_blk;91 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
27 struct dpu_hw_blk base;43 static inline struct dpu_hw_merge_3d *to_dpu_hw_merge_3d(struct dpu_hw_blk *hw) in to_dpu_hw_merge_3d()
48 struct dpu_hw_blk base;61 static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw) in to_dpu_hw_cwb()
60 struct dpu_hw_blk base;76 static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw) in to_dpu_hw_dspp()
54 struct dpu_hw_blk base;79 static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw) in to_dpu_hw_dsc()
114 struct dpu_hw_blk base;129 static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw) in to_dpu_hw_cdm()
70 struct dpu_hw_blk base;91 static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) in to_dpu_hw_mixer()
99 struct dpu_hw_blk base;116 static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) in to_dpu_hw_pingpong()
278 struct dpu_hw_blk base;305 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) in to_dpu_hw_ctl()
150 struct dpu_hw_blk base;
309 struct dpu_hw_blk base;
43 struct dpu_hw_blk { struct
879 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) in dpu_rm_get_assigned_resources()882 struct dpu_hw_blk **hw_blks; in dpu_rm_get_assigned_resources()964 struct dpu_hw_blk *blk, in dpu_rm_print_state_helper()
1156 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()1157 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()1158 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()1159 struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_atomic_mode_set()1231 struct dpu_hw_blk *hw_cdm = NULL; in dpu_encoder_virt_atomic_mode_set()2170 struct dpu_hw_blk *hw_lm[2]; in dpu_encoder_helper_reset_mixers()2335 struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC]; in dpu_encoder_helper_phys_setup_cwb()
1339 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC]; in dpu_crtc_assign_resources()1340 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC]; in dpu_crtc_assign_resources()1341 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC]; in dpu_crtc_assign_resources()