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Searched refs:dpp_base (Results 1 – 23 of 23) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c89 struct dpp *dpp_base, in dpp3_program_post_csc() argument
205 struct dpp *dpp_base, in dpp3_cnv_setup() argument
385 struct dpp *dpp_base, in dpp3_set_cursor_attributes() argument
568 struct dpp *dpp_base, in dpp3_power_on_blnd_lut() argument
588 struct dpp *dpp_base, in dpp3_power_on_hdr3dlut() argument
605 struct dpp *dpp_base, in dpp3_power_on_shaper() argument
622 struct dpp *dpp_base, in dpp3_configure_blnd_lut() argument
635 struct dpp *dpp_base, in dpp3_program_blnd_pwl() argument
699 struct dpp *dpp_base, in dpp3_program_blnd_luta_settings() argument
727 struct dpp *dpp_base, in dpp3_program_blnd_lutb_settings() argument
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H A Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
146 struct dpp *dpp_base, in dpp3_program_cm_dealpha() argument
157 struct dpp *dpp_base, in dpp3_program_cm_bias() argument
202 struct dpp *dpp_base, in dpp3_configure_gamcor_lut() argument
223 dpp3_enable_cm_block(dpp_base); in dpp3_program_gamcor_lut()
231 dpp3_power_on_gamcor_lut(dpp_base, true); in dpp3_program_gamcor_lut()
305 struct dpp *dpp_base, in dpp3_set_hdr_multiplier() argument
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H A Ddcn30_dpp.h591 struct dpp *dpp_base,
594 void dpp30_read_state(struct dpp *dpp_base,
603 struct dpp *dpp_base,
611 struct dpp *dpp_base,
615 struct dpp *dpp_base,
619 struct dpp *dpp_base,
622 void dpp3_set_pre_degam(struct dpp *dpp_base,
626 struct dpp *dpp_base,
630 struct dpp *dpp_base,
636 struct dpp *dpp_base,
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
135 struct dpp *dpp_base, in dpp2_set_degamma() argument
214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap() argument
293 struct dpp *dpp_base, in dpp2_program_input_csc() argument
366 struct dpp *dpp_base, in dpp20_power_on_blnd_lut() argument
377 struct dpp *dpp_base, in dpp20_configure_blnd_lut() argument
390 struct dpp *dpp_base, in dpp20_program_blnd_pwl() argument
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H A Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
78 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
98 struct dpp *dpp_base, in dpp2_cnv_setup() argument
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
255 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
317 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer() argument
320 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_set_alpha_keyer()
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H A Ddcn20_dpp.h713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
734 struct dpp *dpp_base,
738 struct dpp *dpp_base,
742 struct dpp *dpp_base,
759 struct dpp *dpp_base,
763 struct dpp *dpp_base,
772 struct dpp *dpp_base,
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
308 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
378 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
420 struct dpp *dpp_base, in dpp1_cm_configure_regamma_lut() argument
434 struct dpp *dpp_base, in dpp1_cm_program_regamma_luta_settings() argument
463 struct dpp *dpp_base, in dpp1_cm_program_regamma_lutb_settings() argument
490 struct dpp *dpp_base, in dpp1_program_input_csc() argument
566 struct dpp *dpp_base, in dpp1_program_bias_and_scale() argument
587 struct dpp *dpp_base, in dpp1_program_degamma_lutb_settings() argument
616 struct dpp *dpp_base, in dpp1_program_degamma_luta_settings() argument
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H A Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
188 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
197 memset(&dpp_base->pos, 0, sizeof(dpp_base->pos)); in dpp_reset()
198 memset(&dpp_base->att, 0, sizeof(dpp_base->att)); in dpp_reset()
263 struct dpp *dpp_base, in dpp1_set_degamma_format_float() argument
278 struct dpp *dpp_base, in dpp1_cnv_setup() argument
414 struct dpp *dpp_base, in dpp1_set_cursor_attributes() argument
435 struct dpp *dpp_base, in dpp1_set_cursor_position() argument
494 struct dpp *dpp_base, in dpp1_cnv_set_optional_cursor_attributes() argument
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H A Ddcn10_dpp_dscl.c124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
619 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
630 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_dscl_set_scaler_manual_scale()
632 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
659 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) in dpp1_dscl_set_scaler_manual_scale()
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H A Ddcn10_dpp.h1383 struct dpp *dpp_base,
1387 struct dpp *dpp_base,
1409 struct dpp *dpp_base,
1413 struct dpp *dpp_base,
1417 struct dpp *dpp_base,
1421 struct dpp *dpp_base,
1427 struct dpp *dpp_base,
1431 struct dpp *dpp_base,
1437 struct dpp *dpp_base,
1465 struct dpp *dpp_base,
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp_cm.c91 void dpp401_full_bypass(struct dpp *dpp_base) in dpp401_full_bypass() argument
93 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_full_bypass()
116 struct dpp *dpp_base, in dpp401_set_cursor_attributes() argument
119 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_attributes()
143 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp401_set_cursor_attributes()
145 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp401_set_cursor_attributes()
149 struct dpp *dpp_base, in dpp401_set_cursor_position() argument
155 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_set_cursor_position()
166 struct dpp *dpp_base, in dpp401_set_optional_cursor_attributes() argument
181 struct dpp *dpp_base, in dpp401_program_cursor_csc() argument
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H A Ddcn401_dpp_dscl.c126 struct dpp *dpp_base, in dpp401_dscl_get_dscl_mode() argument
160 struct dpp *dpp_base, in dpp401_power_on_dscl() argument
163 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_power_on_dscl()
670 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dscl_program_easf_v()
904 dpp401_dscl_program_easf_v(dpp_base, scl_data); in dpp401_dscl_program_easf()
905 dpp401_dscl_program_easf_h(dpp_base, scl_data); in dpp401_dscl_program_easf()
1075 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp401_dscl_set_scaler_manual_scale()
1116 dpp401_power_on_dscl(dpp_base, true); in dpp401_dscl_set_scaler_manual_scale()
1144 dpp401_power_on_dscl(dpp_base, false); in dpp401_dscl_set_scaler_manual_scale()
1154 dpp401_dscl_disable_easf(dpp_base, scl_data); in dpp401_dscl_set_scaler_manual_scale()
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H A Ddcn401_dpp.c45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state() argument
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state()
56 struct dpp *dpp_base, in dpp401_dpp_setup() argument
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup()
214 dpp3_program_post_csc(dpp_base, color_space, select, in dpp401_dpp_setup()
217 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp401_dpp_setup()
H A Ddcn401_dpp.h683 struct dpp *dpp_base,
686 void dpp401_full_bypass(struct dpp *dpp_base);
689 struct dpp *dpp_base,
697 struct dpp *dpp_base,
701 struct dpp *dpp_base,
708 struct dpp *dpp_base,
724 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);
727 struct dpp *dpp_base,
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h223 struct dpp *dpp_base,
286 struct dpp *dpp_base,
290 struct dpp *dpp_base,
297 struct dpp *dpp_base,
307 struct dpp *dpp_base,
311 struct dpp *dpp_base,
319 struct dpp *dpp_base,
323 struct dpp *dpp_base,
327 struct dpp *dpp_base,
343 struct dpp *dpp_base,
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.c41 struct dpp *dpp_base, in dpp35_dppclk_control() argument
45 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_dppclk_control()
71 struct dpp *dpp_base, in dpp35_program_bias_and_scale_fcnv() argument
74 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp35_program_bias_and_scale_fcnv()
H A Ddcn35_dpp.h53 struct dpp *dpp_base,
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c236 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
238 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
261 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
262 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
313 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
321 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
327 &dpp_base->degamma_params, false)) in dcn30_set_input_transfer_func()
328 params = &dpp_base->degamma_params; in dcn30_set_input_transfer_func()
330 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn30_set_input_transfer_func()
333 if (dpp_base->funcs->dpp_program_blnd_lut) in dcn30_set_input_transfer_func()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
177 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
185 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1067 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
1090 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
1093 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
1121 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn20_set_input_transfer_func()
1126 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn20_set_input_transfer_func()
1137 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
1141 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
1145 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
1151 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn20_set_input_transfer_func()
1159 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut() local
456 &dpp_base->shaper_params, true); in dcn32_set_mpc_shaper_3dlut()
457 shaper_lut = &dpp_base->shaper_params; in dcn32_set_mpc_shaper_3dlut()
490 &dpp_base->regamma_params, false); in dcn32_set_mcm_luts()
494 lut_params = &dpp_base->regamma_params; in dcn32_set_mcm_luts()
506 &dpp_base->shaper_params, true); in dcn32_set_mcm_luts()
507 lut_params = &dpp_base->shaper_params; in dcn32_set_mcm_luts()
541 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn32_set_input_transfer_func()
547 &dpp_base->degamma_params, false)) in dcn32_set_input_transfer_func()
548 params = &dpp_base->degamma_params; in dcn32_set_input_transfer_func()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1822 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1830 dpp_base->funcs->dpp_program_input_lut(dpp_base, &plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1835 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1838 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1841 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1844 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
1846 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
1854 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1857 &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
1858 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn10_set_input_transfer_func()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c404 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts() local
433 &dpp_base->regamma_params, false); in dcn401_populate_mcm_luts()
434 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
453 &dpp_base->regamma_params, true); in dcn401_populate_mcm_luts()
454 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; in dcn401_populate_mcm_luts()
587 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts() local
607 &dpp_base->regamma_params, false); in dcn401_set_mcm_luts()
608 lut_params = rval ? &dpp_base->regamma_params : NULL; in dcn401_set_mcm_luts()
619 &dpp_base->shaper_params, true); in dcn401_set_mcm_luts()
620 lut_params = rval ? &dpp_base->shaper_params : NULL; in dcn401_set_mcm_luts()