Home
last modified time | relevance | path

Searched refs:dpll_hw_state (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c387 if (memcmp(dpll_hw_state, in intel_find_shared_dpll()
389 sizeof(*dpll_hw_state)) == 0) { in intel_find_shared_dpll()
629 &crtc_state->dpll_hw_state, in ibx_get_dpll()
639 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
1057 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
1070 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1843 &crtc_state->dpll_hw_state); in skl_ddi_hdmi_pll_dividers()
1946 &crtc_state->dpll_hw_state, in skl_get_dpll()
1950 &crtc_state->dpll_hw_state, in skl_get_dpll()
4599 ibx_dump_hw_state(p, dpll_hw_state); in intel_dpll_dump_hw_state()
[all …]
H A Dintel_dpll_mgr.h417 const struct intel_dpll_hw_state *dpll_hw_state);
420 struct intel_dpll_hw_state *dpll_hw_state);
431 const struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_dpll.c377 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
390 struct intel_dpll_hw_state *dpll_hw_state) in i9xx_dpll_get_hw_state() argument
393 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
426 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
1080 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1149 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1352 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()
1452 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_compute_dpll()
1478 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_compute_dpll()
1761 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
[all …]
H A Dintel_dpll.h28 struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_cx0_phy.c2085 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2091 intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, in intel_c10pll_calc_state()
2094 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2095 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()
2233 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()
2347 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2349 &crtc_state->dpll_hw_state.cx0pll, in intel_c20pll_calc_state()
2351 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()
3088 __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, in intel_cx0pll_enable()
3383 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; in intel_c10pll_state_verify()
[all …]
H A Dintel_pch_display.c539 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
542 tmp = crtc_state->dpll_hw_state.i9xx.dpll; in ilk_pch_get_config()
H A Dintel_snps_phy.c1801 crtc_state->dpll_hw_state.mpllb = *tables[i]; in intel_mpllb_calc_state()
1808 intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb, in intel_mpllb_calc_state()
1821 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; in intel_mpllb_enable()
1986 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; in intel_mpllb_state_verify()
H A Dintel_crtc_state_dump.c344 intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
H A Dintel_ddi.c4226 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4232 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4234 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4237 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4245 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4246 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4339 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
H A Dintel_display.c1327 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
3047 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); in i9xx_get_pipe_config()
3050 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; in i9xx_get_pipe_config()
3056 tmp = pipe_config->dpll_hw_state.i9xx.dpll; in i9xx_get_pipe_config()
4550 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
5305 PIPE_CONF_CHECK_PLL(dpll_hw_state); in intel_pipe_config_compare()
5309 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); in intel_pipe_config_compare()
H A Dintel_display_types.h1082 struct intel_dpll_hw_state dpll_hw_state; member