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Searched refs:dpll (Results 1 – 25 of 92) sorted by relevance

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/linux-6.15/drivers/dpll/
H A Ddpll_netlink.c199 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_prio() local
270 dpll, dpll_priv(dpll), in dpll_msg_add_pin_phase_adjust()
774 dpll = ref->dpll; in dpll_pin_freq_set()
786 dpll = ref->dpll; in dpll_pin_freq_set()
805 dpll = ref->dpll; in dpll_pin_freq_set()
836 dpll = ref->dpll; in dpll_pin_esync_set()
858 dpll = ref->dpll; in dpll_pin_esync_set()
881 dpll = ref->dpll; in dpll_pin_esync_set()
1041 dpll = ref->dpll; in dpll_pin_phase_adj_set()
1054 dpll = ref->dpll; in dpll_pin_phase_adj_set()
[all …]
H A Ddpll_core.c164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
248 dpll = kzalloc(sizeof(*dpll), GFP_KERNEL); in dpll_device_alloc()
249 if (!dpll) in dpll_device_alloc()
256 ret = xa_alloc_cyclic(&dpll_device_xa, &dpll->id, dpll, xa_limit_32b, in dpll_device_alloc()
259 kfree(dpll); in dpll_device_alloc()
264 return dpll; in dpll_device_alloc()
292 ret = dpll; in dpll_device_get()
322 kfree(dpll); in dpll_device_put()
[all …]
H A DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
H A Ddpll_core.h73 struct dpll_device *dpll; member
80 void *dpll_priv(struct dpll_device *dpll);
81 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);
84 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
H A Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c332 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
427 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local
988 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
990 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
995 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1010 u32 dpll; in i9xx_dpll() local
1260 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1921 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
2049 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2226 const struct dpll *dpll) in vlv_force_pll_on() argument
[all …]
H A Dintel_dpll.h11 struct dpll;
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
33 const struct dpll *dpll);
43 struct dpll *best_clock);
44 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll_mgr.c540 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
653 hw_state->dpll, in ibx_dump_hw_state()
665 return a->dpll == b->dpll && in ibx_compare_hw_state()
2257 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers()
2275 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers()
2367 struct dpll clock; in bxt_ddi_pll_get_freq()
2384 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state()
2395 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state()
4539 if (display->dpll.mgr && display->dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4593 if (display->dpll.mgr) { in intel_dpll_dump_hw_state()
[all …]
H A Dg4x_dp.h21 const struct dpll *vlv_get_dpll(struct intel_display *display);
28 static inline const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll()
/linux-6.15/include/linux/
H A Ddpll.h37 const struct dpll_device *dpll, void *dpll_priv,
57 const struct dpll_device *dpll,
66 const struct dpll_device *dpll,
71 const struct dpll_device *dpll, void *dpll_priv,
74 const struct dpll_device *dpll, void *dpll_priv,
77 const struct dpll_device *dpll, void *dpll_priv,
81 const struct dpll_device *dpll, void *dpll_priv,
85 const struct dpll_device *dpll, void *dpll_priv,
92 const struct dpll_device *dpll, void *dpll_priv,
95 const struct dpll_device *dpll, void *dpll_priv,
[all …]
/linux-6.15/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c168 dpll |= in psb_intel_crtc_mode_set()
192 dpll |= 3; in psb_intel_crtc_mode_set()
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
256 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
261 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
310 u32 dpll; in psb_intel_crtc_clock_get() local
317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
325 dpll = p->dpll; in psb_intel_crtc_clock_get()
342 ffs((dpll & in psb_intel_crtc_clock_get()
[all …]
H A Doaktrail_crtc.c251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
533 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set()
541 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set()
542 dpll |= in oaktrail_crtc_mode_set()
554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
[all …]
H A Dcdv_intel_display.c665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
842 u32 dpll; in cdv_intel_crtc_clock_get() local
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
857 dpll = p->dpll; in cdv_intel_crtc_clock_get()
873 ffs((dpll & in cdv_intel_crtc_clock_get()
[all …]
H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
634 REG_WRITE(map->dpll, in gma_crtc_restore()
636 REG_READ(map->dpll); in gma_crtc_restore()
[all …]
/linux-6.15/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
25 "ti,omap5-mpu-dpll-clock",
27 "ti,am3-dpll-j-type-clock",
29 "ti,am3-dpll-clock",
30 "ti,am3-dpll-core-clock",
[all …]
/linux-6.15/Documentation/driver-api/
H A Ddpll.rst4 The Linux kernel dpll subsystem
53 provided for a single dpll device.
115 being directly registered to a dpll device.
180 on a pin and its parent dpll device. If pin-dpll phase offset measurement
182 attribute for each parent dpll device.
210 a dpll.
411 .. kernel-doc:: include/uapi/linux/dpll.h
521 if (IS_ERR(bp->dpll)) {
522 err = PTR_ERR(bp->dpll);
555 dpll_device_put(bp->dpll);
[all …]
/linux-6.15/Documentation/netlink/specs/
H A Ddpll.yaml3 name: dpll
12 working modes a dpll can support, differentiates if and how dpll selects
246 name: dpll
447 attribute-set: dpll
451 pre: dpll-lock-doit
466 attribute-set: dpll
470 pre: dpll-pre-doit
471 post: dpll-post-doit
493 attribute-set: dpll
497 pre: dpll-pre-doit
[all …]
/linux-6.15/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c526 dpll->input_prio[pin->idx] = prio; in ice_dpll_hw_input_prio_set()
1488 dpll_device_change_ntf(d->dpll); in ice_dpll_notify_changes()
1935 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
1943 pf->dplls.eec.dpll, in ice_dpll_init_pins()
1944 pf->dplls.pps.dpll); in ice_dpll_init_pins()
1959 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1963 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1981 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll()
2006 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll()
2007 ret = PTR_ERR(d->dpll); in ice_dpll_init_dpll()
[all …]
/linux-6.15/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c11 struct dpll_device *dpll; member
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
352 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
442 if (IS_ERR(mdpll->dpll)) { in mlx5_dpll_probe()
443 err = PTR_ERR(mdpll->dpll); in mlx5_dpll_probe()
479 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_probe()
486 dpll_device_put(mdpll->dpll); in mlx5_dpll_probe()
500 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_remove()
[all …]
/linux-6.15/Documentation/devicetree/bindings/media/i2c/
H A Dadv748x.yaml38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
[all …]
/linux-6.15/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
313 dpll_core_x2_ck: clock-dpll-core-x2 {
398 compatible = "ti,omap4-dpll-clock";
448 compatible = "ti,omap4-dpll-clock";
498 compatible = "ti,omap4-dpll-clock";
560 compatible = "ti,omap4-dpll-clock";
597 compatible = "ti,omap4-dpll-clock";
688 compatible = "ti,omap4-dpll-clock";
775 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
794 dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
[all …]
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
331 compatible = "ti,am3-dpll-clock";
352 compatible = "ti,am3-dpll-j-type-clock";
635 compatible = "ti,am3-dpll-clock";
711 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
[all …]
H A Dam33xx-clocks.dtsi191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
287 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
[all …]
/linux-6.15/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";

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