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Searched refs:dp_phy (Results 1 – 23 of 23) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c71 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
78 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
488 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
494 lt_dbg(intel_dp, dp_phy, in intel_dp_get_adjust_train()
520 enum drm_dp_phy dp_phy, in intel_dp_set_link_train() argument
595 enum drm_dp_phy dp_phy) in intel_dp_set_signal_levels() argument
600 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
606 lt_dbg(intel_dp, dp_phy, in intel_dp_set_signal_levels()
838 lt_dbg(intel_dp, dp_phy, in intel_dp_dump_link_status()
1128 enum drm_dp_phy dp_phy) in intel_dp_link_train_phy() argument
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H A Dintel_dp_link_training.h28 enum drm_dp_phy dp_phy,
32 enum drm_dp_phy dp_phy,
36 enum drm_dp_phy dp_phy);
44 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
/linux-6.15/drivers/phy/mediatek/
H A Dphy-mtk-dp.c87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
150 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
166 struct mtk_dp_phy *dp_phy; in mtk_dp_phy_probe() local
175 dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); in mtk_dp_phy_probe()
176 if (!dp_phy) in mtk_dp_phy_probe()
179 dp_phy->regs = regs; in mtk_dp_phy_probe()
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/linux-6.15/include/drm/display/
H A Ddrm_dp.h1517 #define DP_LTTPR_BASE(dp_phy) \ argument
1519 ((dp_phy) - DP_PHY_LTTPR1))
1521 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1549 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ argument
1563 #define DP_OUI_PHY_REPEATER(dp_phy) \ argument
1564 DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1)
1568 #define DP_FEC_BASE(dp_phy) \ argument
1570 ((dp_phy) - DP_PHY_LTTPR1)))
1572 #define DP_FEC_REG(dp_phy, fec1_reg) \ argument
1576 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ argument
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H A Ddrm_dp_helper.h48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
567 enum drm_dp_phy dp_phy,
629 enum drm_dp_phy dp_phy,
669 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
/linux-6.15/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c287 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
293 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
342 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
349 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
432 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || in drm_dp_phy_name()
433 WARN_ON(!phy_names[dp_phy])) in drm_dp_phy_name()
436 return phy_names[dp_phy]; in drm_dp_phy_name()
802 enum drm_dp_phy dp_phy, in drm_dp_dpcd_read_phy_link_status() argument
807 if (dp_phy == DP_PHY_DPRX) { in drm_dp_dpcd_read_phy_link_status()
2582 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) in drm_dp_dump_lttpr_desc()
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/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dqcom,sc7180-dispcc.yaml62 <&dp_phy 0>,
63 <&dp_phy 1>;
H A Dqcom,dispcc-sm6350.yaml62 <&dp_phy 0>,
63 <&dp_phy 1>;
H A Dqcom,sc7280-dispcc.yaml66 <&dp_phy 0>,
67 <&dp_phy 1>,
H A Dqcom,sm7150-dispcc.yaml68 <&dp_phy 0>,
69 <&dp_phy 1>;
H A Dqcom,sdm845-dispcc.yaml74 <&dp_phy 0>,
75 <&dp_phy 1>;
H A Dqcom,dispcc-sm6125.yaml87 <&dp_phy 0>,
88 <&dp_phy 1>,
H A Dqcom,dispcc-sm8x50.yaml108 <&dp_phy 0>,
109 <&dp_phy 1>;
/linux-6.15/Documentation/devicetree/bindings/display/msm/
H A Ddp-controller.yaml208 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
210 phys = <&dp_phy>;
H A Dqcom,sc7180-mdss.yaml272 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
273 phys = <&dp_phy>;
H A Dqcom,sc7280-mdss.yaml392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
393 phys = <&dp_phy>;
H A Dqcom,sm7150-mdss.yaml404 assigned-clock-parents = <&dp_phy 0>,
405 <&dp_phy 1>;
410 phys = <&dp_phy>;
/linux-6.15/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,analogix-dp.yaml68 phys = <&dp_phy>;
/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,mhdp8546.yaml140 phys = <&dp_phy>;
/linux-6.15/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml144 phys = <&dp_phy>;
/linux-6.15/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-combo.c1693 struct phy *dp_phy; member
3753 return qmp->dp_phy; in qmp_combo_phy_xlate()
3840 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3841 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3842 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3847 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos5250.dtsi298 dp_phy: dp-phy { label
1126 phys = <&dp_phy>;
H A Dexynos5420.dtsi933 dp_phy: dp-phy { label
1213 phys = <&dp_phy>;