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Searched refs:dp_m_n (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp_mst.c308 &crtc_state->dp_m_n); in intel_dp_mtp_tu_compute_config()
355 drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu); in intel_dp_mtp_tu_compute_config()
356 crtc_state->dp_m_n.tu = remote_tu; in intel_dp_mtp_tu_compute_config()
363 crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu, in intel_dp_mtp_tu_compute_config()
366 if (crtc_state->dp_m_n.tu <= 64) in intel_dp_mtp_tu_compute_config()
367 slots = crtc_state->dp_m_n.tu; in intel_dp_mtp_tu_compute_config()
376 drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu); in intel_dp_mtp_tu_compute_config()
696 pipe_config->dp_m_n.tu); in mst_stream_compute_config()
H A Dintel_drrs.c168 crtc->drrs.m_n = crtc_state->dp_m_n; in intel_drrs_activate()
H A Dg4x_dp.c327 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); in g4x_dp_get_m_n()
331 &crtc_state->dp_m_n); in g4x_dp_get_m_n()
406 &pipe_config->dp_m_n); in intel_dp_get_config()
H A Dintel_crtc_state_dump.c236 &pipe_config->dp_m_n); in intel_crtc_state_dump()
H A Dintel_pch_display.c413 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); in ilk_pch_enable()
H A Dintel_display.c1498 &crtc_state->dp_m_n); in ilk_configure_cpu_transcoder()
1630 &crtc_state->dp_m_n); in hsw_configure_cpu_transcoder()
2022 &crtc_state->dp_m_n); in i9xx_configure_cpu_transcoder()
4029 &pipe_config->dp_m_n); in intel_crtc_dotclock()
5211 PIPE_CONF_CHECK_M_N(dp_m_n); in intel_pipe_config_compare()
5213 PIPE_CONF_CHECK_M_N(dp_m_n); in intel_pipe_config_compare()
5701 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, in intel_crtc_check_fastset()
5702 &new_crtc_state->dp_m_n)) in intel_crtc_check_fastset()
6573 &new_crtc_state->dp_m_n); in intel_pipe_fastset()
H A Dintel_ddi.c2721 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in mtl_ddi_pre_enable_dp()
2869 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in tgl_ddi_pre_enable_dp()
4037 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_sst()
4073 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_mst()
4494 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
H A Dintel_display_types.h1101 struct intel_link_m_n dp_m_n; member
H A Dintel_dp.c3203 &pipe_config->dp_m_n); in intel_dp_compute_config()
3208 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; in intel_dp_compute_config()