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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c186 dlg_regs->refcyc_h_blank_end); in print__dlg_regs_st()
189 dlg_regs->dlg_vblank_end); in print__dlg_regs_st()
195 dlg_regs->refcyc_per_htotal); in print__dlg_regs_st()
201 dlg_regs->dst_y_after_scaler); in print__dlg_regs_st()
204 dlg_regs->dst_y_prefetch); in print__dlg_regs_st()
207 dlg_regs->dst_y_per_vm_vblank); in print__dlg_regs_st()
213 dlg_regs->dst_y_per_vm_flip); in print__dlg_regs_st()
216 dlg_regs->dst_y_per_row_flip); in print__dlg_regs_st()
222 dlg_regs->vratio_prefetch); in print__dlg_regs_st()
225 dlg_regs->vratio_prefetch_c); in print__dlg_regs_st()
[all …]
H A Ddisplay_mode_lib.h53 display_dlg_regs_st *dlg_regs,
71 display_dlg_regs_st *dlg_regs,
H A Ddml1_display_rq_dlg_calc.h56 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
H A Ddisplay_rq_dlg_helpers.h42 …lg_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_regs_st *dlg_regs);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c207 display_dlg_regs_st *dlg_regs, in dml32_rq_dlg_get_dlg_reg() argument
266 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dml32_rq_dlg_get_dlg_reg()
290 dlg_regs->vready_after_vcount0 = vready_after_vcount0; in dml32_rq_dlg_get_dlg_reg()
525 dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml32_rq_dlg_get_dlg_reg()
526 dlg_regs->dst_y_offset_cur0 = 0; in dml32_rq_dlg_get_dlg_reg()
527 dlg_regs->chunk_hdl_adjust_cur1 = 3; in dml32_rq_dlg_get_dlg_reg()
528 dlg_regs->dst_y_offset_cur1 = 0; in dml32_rq_dlg_get_dlg_reg()
530 dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off in dml32_rq_dlg_get_dlg_reg()
569 dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; in dml32_rq_dlg_get_dlg_reg()
571 ASSERT(dlg_regs->dst_y_after_scaler < (unsigned int) 8); in dml32_rq_dlg_get_dlg_reg()
[all …]
H A Ddisplay_rq_dlg_calc_32.h64 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c261 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_get_dlg_states()
262 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_get_dlg_states()
263 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_get_dlg_states()
264 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_get_dlg_states()
265 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_get_dlg_states()
269 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_get_dlg_states()
270 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, in dcn10_get_dlg_states()
271 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, in dcn10_get_dlg_states()
275 …dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, in dcn10_get_dlg_states()
276 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_get_dlg_states()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.c249 void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs) in dml_print_dlg_regs_st() argument
253 dml_print("DML: refcyc_h_blank_end = 0x%x\n", dlg_regs->refcyc_h_blank_end); in dml_print_dlg_regs_st()
254 dml_print("DML: dlg_vblank_end = 0x%x\n", dlg_regs->dlg_vblank_end); in dml_print_dlg_regs_st()
256 dml_print("DML: refcyc_per_htotal = 0x%x\n", dlg_regs->refcyc_per_htotal); in dml_print_dlg_regs_st()
258 dml_print("DML: dst_y_after_scaler = 0x%x\n", dlg_regs->dst_y_after_scaler); in dml_print_dlg_regs_st()
259 dml_print("DML: dst_y_prefetch = 0x%x\n", dlg_regs->dst_y_prefetch); in dml_print_dlg_regs_st()
262 dml_print("DML: dst_y_per_vm_flip = 0x%x\n", dlg_regs->dst_y_per_vm_flip); in dml_print_dlg_regs_st()
263 dml_print("DML: dst_y_per_row_flip = 0x%x\n", dlg_regs->dst_y_per_row_flip); in dml_print_dlg_regs_st()
265 dml_print("DML: vratio_prefetch = 0x%x\n", dlg_regs->vratio_prefetch); in dml_print_dlg_regs_st()
266 dml_print("DML: vratio_prefetch_c = 0x%x\n", dlg_regs->vratio_prefetch_c); in dml_print_dlg_regs_st()
[all …]
H A Ddml2_translation_helper.c1474 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs)); in dml2_update_pipe_ctx_dchub_regs()
1475 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end; in dml2_update_pipe_ctx_dchub_regs()
1476 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end; in dml2_update_pipe_ctx_dchub_regs()
1478 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal; in dml2_update_pipe_ctx_dchub_regs()
1481 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1484 out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip; in dml2_update_pipe_ctx_dchub_regs()
1487 out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch; in dml2_update_pipe_ctx_dchub_regs()
1488 out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c; in dml2_update_pipe_ctx_dchub_regs()
1513 out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0; in dml2_update_pipe_ctx_dchub_regs()
1515 out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1; in dml2_update_pipe_ctx_dchub_regs()
[all …]
H A Ddml_display_rq_dlg_calc.h55 void dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st *dlg_regs,
H A Ddisplay_mode_util.h56 __DML_DLL_EXPORT__ void dml_print_dlg_regs_st(const dml_display_dlg_regs_st *dlg_regs);
/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c320 hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); in hubp401_setup()
330 DST_Y_PREFETCH, pipe_regs->dlg_regs.dst_y_prefetch, in hubp401_setup_interdependent()
331 VRATIO_PREFETCH, pipe_regs->dlg_regs.vratio_prefetch); in hubp401_setup_interdependent()
334 VRATIO_PREFETCH_C, pipe_regs->dlg_regs.vratio_prefetch_c); in hubp401_setup_interdependent()
337 DST_Y_PER_VM_VBLANK, pipe_regs->dlg_regs.dst_y_per_vm_vblank, in hubp401_setup_interdependent()
338 DST_Y_PER_ROW_VBLANK, pipe_regs->dlg_regs.dst_y_per_row_vblank); in hubp401_setup_interdependent()
341 DST_Y_PER_VM_FLIP, pipe_regs->dlg_regs.dst_y_per_vm_flip, in hubp401_setup_interdependent()
342 DST_Y_PER_ROW_FLIP, pipe_regs->dlg_regs.dst_y_per_row_flip); in hubp401_setup_interdependent()
345 REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l); in hubp401_setup_interdependent()
351 REFCYC_PER_META_CHUNK_FLIP_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_flip_l); in hubp401_setup_interdependent()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c246 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_log_hubp_states()
247 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler, in dcn10_log_hubp_states()
248 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank, in dcn10_log_hubp_states()
249 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq, in dcn10_log_hubp_states()
250 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l, in dcn10_log_hubp_states()
254 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l, in dcn10_log_hubp_states()
255 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l, in dcn10_log_hubp_states()
256 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l, in dcn10_log_hubp_states()
260 …dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, in dcn10_log_hubp_states()
261 … dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit, in dcn10_log_hubp_states()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.h62 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.h62 display_dlg_regs_st *dlg_regs,
H A Ddisplay_rq_dlg_calc_20v2.h62 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h59 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h58 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.h58 display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhubp.h143 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
156 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
H A Dmem_input.h107 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_dchub_registers.h149 struct dml2_display_dlg_regs dlg_regs; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; in dcn_bw_calc_rq_dlg_ttu() local
470 memset(dlg_regs, 0, sizeof(*dlg_regs)); in dcn_bw_calc_rq_dlg_ttu()
511 dlg_regs, in dcn_bw_calc_rq_dlg_ttu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h458 struct _vcs_dpi_display_dlg_regs_st dlg_regs; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1602 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1604 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; in dcn20_detect_pipe_changes()
1647 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || in dcn20_detect_pipe_changes()
1698 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
1716 &pipe_ctx->dlg_regs, in dcn20_update_dchubp_dpp()
2472 pipe_ctx->dlg_regs.min_dst_y_next_start); in dcn20_optimize_bandwidth()
2521 &pipe_ctx->dlg_regs, in dcn20_update_bandwidth()

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