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/linux-6.15/drivers/clk/tegra/
H A Dclk-divider.c27 divider->frac_width, divider->flags); in get_div()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
92 if (divider->lock) in clk_frac_div_set_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
111 if (divider->lock) in clk_frac_div_set_rate()
143 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in tegra_clk_register_divider()
144 if (!divider) { in tegra_clk_register_divider()
156 divider->reg = reg; in tegra_clk_register_divider()
160 divider->lock = lock; in tegra_clk_register_divider()
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/linux-6.15/drivers/clk/ti/
H A Ddivider.c38 if (divider->table) { in _setup_mask()
66 if (divider->table) in _get_div()
88 if (divider->table) in _get_val()
99 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
134 if (divider->table) in _is_valid_div()
257 val &= ~(divider->mask << divider->shift); in ti_clk_divider_set_rate()
261 ti_clk_latch(&divider->reg, divider->latch); in ti_clk_divider_set_rate()
277 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in clk_divider_save_context()
278 divider->context = val & divider->mask; in clk_divider_save_context()
295 val &= ~(divider->mask << divider->shift); in clk_divider_restore_context()
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H A Dclk-dra7-atl.c49 u32 divider; /* Cached divider value */ member
85 cdesc->divider - 1); in atl_clk_enable()
120 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
126 unsigned divider; in atl_clk_round_rate() local
130 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
132 return *parent_rate / divider; in atl_clk_round_rate()
139 u32 divider; in atl_clk_set_rate() local
146 if (divider > DRA7_ATL_DIVIDER_MASK) in atl_clk_set_rate()
147 divider = DRA7_ATL_DIVIDER_MASK; in atl_clk_set_rate()
149 cdesc->divider = divider + 1; in atl_clk_set_rate()
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/linux-6.15/drivers/clk/qcom/
H A Dclk-regmap-divider.c22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
53 (BIT(divider->width) - 1) << divider->shift, in div_set_rate()
54 div << divider->shift); in div_set_rate()
61 struct clk_regmap *clkr = &divider->clkr; in div_recalc_rate()
64 regmap_read(clkr->regmap, divider->reg, &div); in div_recalc_rate()
65 div >>= divider->shift; in div_recalc_rate()
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/linux-6.15/drivers/clk/mvebu/
H A Ddove-divider.c62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
93 divider = 1; in dove_calc_divider()
96 return divider; in dove_calc_divider()
116 int divider; in dove_round_rate() local
119 if (divider < 0) in dove_round_rate()
120 return divider; in dove_round_rate()
135 int divider; in dove_set_clock() local
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/linux-6.15/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c200 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate_ver()
225 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate()
232 divider->flags, divider->width); in clk_wzrd_recalc_rate()
239 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_ver_dynamic_reconfig()
287 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_dynamic_reconfig()
407 divider->m_frac = (m - (divider->m << 3)) * 125; in clk_wzrd_get_divisors()
410 divider->o_frac = (o - (divider->o << 3)) * 125; in clk_wzrd_get_divisors()
642 divider->flags, divider->width); in clk_wzrd_recalc_rate_all_ver()
682 divider->flags, divider->width); in clk_wzrd_ver_round_rate_all()
721 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_ratef()
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/linux-6.15/drivers/clk/
H A Dclk-divider.c161 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
165 divider->flags, divider->width); in clk_divider_recalc_rate()
443 val = clk_div_readl(divider) >> divider->shift; in clk_divider_round_rate()
447 divider->width, divider->flags, in clk_divider_round_rate()
452 divider->width, divider->flags); in clk_divider_round_rate()
464 val = clk_div_readl(divider) >> divider->shift; in clk_divider_determine_rate()
502 divider->width, divider->flags); in clk_divider_set_rate()
506 if (divider->lock) in clk_divider_set_rate()
512 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
515 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
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H A Dclk-milbeaut.c382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
402 divider->width, divider->flags, in m10v_clk_divider_round_rate()
407 divider->width, divider->flags); in m10v_clk_divider_round_rate()
420 divider->width, divider->flags); in m10v_clk_divider_set_rate()
424 if (divider->lock) in m10v_clk_divider_set_rate()
427 __acquire(divider->lock); in m10v_clk_divider_set_rate()
429 val = readl(divider->reg); in m10v_clk_divider_set_rate()
430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
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/linux-6.15/drivers/clk/rockchip/
H A Dclk-half-divider.c28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
123 __acquire(divider->lock); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
128 val = readl(divider->reg); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
132 writel(val, divider->reg); in clk_half_divider_set_rate()
134 if (divider->lock) in clk_half_divider_set_rate()
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/linux-6.15/drivers/clk/mxs/
H A Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
94 div->divider.lock = &mxs_lock; in mxs_clk_div()
95 div->divider.hw.init = &init; in mxs_clk_div()
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/linux-6.15/drivers/clk/imx/
H A Dclk-fixup-div.c24 struct clk_divider divider; member
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
112 fixup_div->divider.width = width; in imx_clk_hw_fixup_divider()
113 fixup_div->divider.lock = &imx_ccm_lock; in imx_clk_hw_fixup_divider()
114 fixup_div->divider.hw.init = &init; in imx_clk_hw_fixup_divider()
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H A Dclk-composite-8m.c36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
110 val = orig & ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
117 writel(val, divider->reg); in imx8m_clk_composite_divider_set_rate()
135 val = readl(divider->reg); in imx8m_divider_determine_rate()
136 prediv_value = val >> divider->shift; in imx8m_divider_determine_rate()
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H A Dclk-composite-93.c116 struct clk_divider *divider = to_clk_divider(hw); in imx93_clk_composite_divider_set_rate() local
122 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
126 if (divider->lock) in imx93_clk_composite_divider_set_rate()
127 spin_lock_irqsave(divider->lock, flags); in imx93_clk_composite_divider_set_rate()
129 val = readl(divider->reg); in imx93_clk_composite_divider_set_rate()
130 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
131 val |= (u32)value << divider->shift; in imx93_clk_composite_divider_set_rate()
132 writel(val, divider->reg); in imx93_clk_composite_divider_set_rate()
134 ret = imx93_clk_composite_wait_ready(hw, divider->reg); in imx93_clk_composite_divider_set_rate()
136 if (divider->lock) in imx93_clk_composite_divider_set_rate()
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H A Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
/linux-6.15/drivers/clk/stm32/
H A Dclk-stm32-core.c216 val = readl(base + divider->offset) >> divider->shift; in stm32_divider_get_rate()
218 div = _get_div(divider->table, val, divider->flags, divider->width); in stm32_divider_get_rate()
240 divider->width, divider->flags); in stm32_divider_set_rate()
245 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()
248 val &= ~(clk_div_mask(divider->width) << divider->shift); in stm32_divider_set_rate()
369 val = readl(div->base + divider->offset) >> divider->shift; in clk_stm32_divider_round_rate()
373 divider->width, divider->flags, in clk_stm32_divider_round_rate()
379 divider->width, divider->flags); in clk_stm32_divider_round_rate()
447 val = readl(composite->base + divider->offset) >> divider->shift; in clk_stm32_composite_determine_rate()
451 divider->table, divider->width, divider->flags, in clk_stm32_composite_determine_rate()
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/linux-6.15/drivers/clk/zynqmp/
H A Ddivider.c84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
100 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
127 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
128 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
134 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
145 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
151 width = fls(divider->max_div); in zynqmp_clk_divider_round_rate()
174 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate()
175 u32 div_type = divider->div_type; in zynqmp_clk_divider_set_rate()
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/linux-6.15/drivers/clk/baikal-t1/
H A Dccu-div.c211 unsigned long divider; in ccu_div_var_recalc_rate() local
224 unsigned long divider; in ccu_div_var_calc_divider() local
235 unsigned long divider; in ccu_div_var_round_rate() local
257 divider = 0; in ccu_div_var_set_rate_slow()
259 if (divider == 1 || divider == 2) in ccu_div_var_set_rate_slow()
260 divider = 0; in ccu_div_var_set_rate_slow()
261 else if (divider == 3) in ccu_div_var_set_rate_slow()
262 divider = 4; in ccu_div_var_set_rate_slow()
428 *val = div->divider; in ccu_div_dbgfs_fixed_clkdiv_get()
611 div->divider = div_init->divider; in ccu_div_hw_register()
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/linux-6.15/Documentation/devicetree/bindings/iio/afe/
H A Dvoltage-divider.yaml4 $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
7 title: Voltage divider
13 When an io-channel measures the midpoint of a voltage divider, the
15 of the divider. This binding describes the voltage divider in such
35 const: voltage-divider
45 output channel, the voltage divider can act as a provider of
48 such as a voltage divider, and then consuming its raw value
49 isn't interesting. In this case, the voltage before the divider
59 Resistance R + Rout for the full divider. The io-channel is scaled by
75 * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
[all …]
/linux-6.15/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c165 val = divider->initval; in sg2042_clk_divider_recalc_rate()
167 val = readl(divider->reg) >> divider->shift; in sg2042_clk_divider_recalc_rate()
172 divider->div_flags, divider->width); in sg2042_clk_divider_recalc_rate()
192 bestdiv = readl(divider->reg) >> divider->shift; in sg2042_clk_divider_round_rate()
198 divider->width, divider->div_flags); in sg2042_clk_divider_round_rate()
215 divider->width, divider->div_flags); in sg2042_clk_divider_set_rate()
217 if (divider->lock) in sg2042_clk_divider_set_rate()
220 __acquire(divider->lock); in sg2042_clk_divider_set_rate()
235 val = clk_div_mask(divider->width) << (divider->shift + 16); in sg2042_clk_divider_set_rate()
238 val &= ~(clk_div_mask(divider->width) << divider->shift); in sg2042_clk_divider_set_rate()
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/linux-6.15/drivers/clk/davinci/
H A Dpll.c253 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
254 if (!divider) { in davinci_pll_div_register()
259 divider->reg = reg; in davinci_pll_div_register()
279 kfree(divider); in davinci_pll_div_register()
599 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_obsclk_register()
600 if (!divider) { in davinci_pll_obsclk_register()
628 kfree(divider); in davinci_pll_obsclk_register()
700 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_sysclk_register()
701 if (!divider) { in davinci_pll_sysclk_register()
709 divider->flags = 0; in davinci_pll_sysclk_register()
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/linux-6.15/Documentation/devicetree/bindings/regulator/
H A Dlltc,ltc3676.yaml48 lltc,fb-voltage-divider:
51 R1 and R2 of the feedback voltage divider in ohms.
57 - lltc,fb-voltage-divider
70 lltc,fb-voltage-divider:
73 R1 and R2 of the feedback voltage divider in ohms.
79 - lltc,fb-voltage-divider
111 lltc,fb-voltage-divider = <127000 200000>;
120 lltc,fb-voltage-divider = <301000 200000>;
129 lltc,fb-voltage-divider = <127000 200000>;
138 lltc,fb-voltage-divider = <221000 200000>;
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/linux-6.15/Documentation/devicetree/bindings/clock/ti/
H A Dti,divider-clock.yaml4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
7 title: Texas Instruments divider clock
13 This clock It assumes a register-mapped adjustable clock rate divider
65 - ti,divider-clock
66 - ti,composite-divider-clock
88 number of bits to shift the divider value
141 latch the divider value to HW, only needed if the register
143 H14 divider implements such behavior.
169 compatible = "ti,divider-clock";
178 compatible = "ti,divider-clock";
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/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
27 reg-names = "control", "multiplier", "post-divider";
64 - compatible : shall be "ti,keystone,pll-divider-clock"
68 - bit-mask : arbitrary bitmask for programming the divider
76 compatible = "ti,keystone,pll-divider-clock";
/linux-6.15/drivers/i2c/busses/
H A Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
100 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
101 divider++; in clk_bcm2835_i2c_calc_divider()
102 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
103 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
106 return divider; in clk_bcm2835_i2c_calc_divider()
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
126 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
132 redl = max(divider / 4, 1u); in clk_bcm2835_i2c_set_rate()
145 return DIV_ROUND_UP(*parent_rate, divider); in clk_bcm2835_i2c_round_rate()
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