| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 3666 display_cfg, in CalculateDCFCLKDeepSleep()
5084 display_cfg, in CalculateExtraLatency()
8278 display_cfg, in dml_core_mode_support()
8346 CalculateVMRowAndSwath_params->display_cfg = display_cfg; in dml_core_mode_support()
8563 display_cfg, in dml_core_mode_support()
8851 display_cfg, in dml_core_mode_support()
9464 CalculateWatermarks_params->display_cfg = display_cfg; in dml_core_mode_support()
10589 display_cfg, in dml_core_mode_programming()
10761 CalculateVMRowAndSwath_params->display_cfg = display_cfg; in dml_core_mode_programming()
10972 display_cfg, in dml_core_mode_programming()
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| H A D | dml2_core_utils.c | 337 for (unsigned int k = 0; k < display_cfg->num_planes; k++) { in dml2_core_utils_get_stream_output_bpp()
338 …double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
339 …if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.ena… in dml2_core_utils_get_stream_output_bpp()
340 …switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.out… in dml2_core_utils_get_stream_output_bpp()
355 …} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.… in dml2_core_utils_get_stream_output_bpp()
356 …out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_inde… in dml2_core_utils_get_stream_output_bpp()
362 …2_printf("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg… in dml2_core_utils_get_stream_output_bpp()
621 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in dml2_core_utils_expand_implict_subvp()
625 if (!display_cfg->stage3.performed) { in dml2_core_utils_expand_implict_subvp()
635 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in dml2_core_utils_expand_implict_subvp()
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| H A D | dml2_core_dcn4_calcs.h | 21 void dml2_core_calcs_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
22 void dml2_core_calcs_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_c…
27 void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struc…
29 void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const stru…
31 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, union dmub_cmd…
32 …splay_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, struct dmub_cm…
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| H A D | dml2_core_dcn4.c | 202 if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) in expand_implict_subvp()
206 if (!display_cfg->stage3.performed) { in expand_implict_subvp()
216 if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { in expand_implict_subvp()
219 main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); in expand_implict_subvp()
232 main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; in expand_implict_subvp()
275 if (display_cfg->stage3.performed && display_cfg->stage3.success) { in pack_mode_programming_params_with_implicit_subvp()
276 programming->fams2_required = display_cfg->stage3.fams2_required; in pack_mode_programming_params_with_implicit_subvp()
320 if (display_cfg->stage3.performed && display_cfg->stage3.success) { in pack_mode_programming_params_with_implicit_subvp()
329 &display_cfg->stage2.mcache_allocations[plane_index], in pack_mode_programming_params_with_implicit_subvp()
352 display_cfg, in pack_mode_programming_params_with_implicit_subvp()
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| H A D | dml2_core_utils.h | 18 …dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg,…
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| H A D | dml2_core_shared_types.h | 1142 const struct dml2_display_cfg *display_cfg; member
1267 const struct dml2_display_cfg *display_cfg; member
1492 const struct dml2_display_cfg *display_cfg; member
1546 const struct dml2_display_cfg *display_cfg; member
1598 const struct dml2_display_cfg *display_cfg; member
1684 const struct dml2_display_cfg *display_cfg; member
1736 const struct dml2_display_cfg *display_cfg; member
2025 const struct dml2_display_cfg *display_cfg; member
2058 const struct dml2_display_cfg *display_cfg; member
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 29 if (in_out->display_cfg->stage3.success) in get_minimum_clocks_for_latency()
60 if (in_out->display_cfg->display_config.hostvm_enable) in calculate_system_active_minimums()
313 display_cfg->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz = 0; in map_soc_min_clocks_to_dpm_fine_grained()
355 display_cfg->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
356 display_cfg->min_clocks.dcn4x.svp_prefetch.fclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
357 display_cfg->min_clocks.dcn4x.svp_prefetch.uclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
368 if (!state_table || !display_cfg) in map_min_clocks_to_dpm()
400 for (i = 0; i < display_cfg->display_config.num_streams; i++) { in map_min_clocks_to_dpm()
699 if (in_out->display_cfg->stage3.success) in dpmm_dcn4_map_mode_to_soc_dpm()
747 const struct dml2_display_cfg *display_cfg = &in_out->display_cfg->display_config; in dpmm_dcn4_map_watermarks() local
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/ |
| H A D | dml2_pmo_dcn4_fams2.c | 236 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
237 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
1288 const struct display_configuation_with_meta *display_cfg, in is_timing_group_schedulable() argument
1315 for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { in is_timing_group_schedulable()
1348 const struct display_configuation_with_meta *display_cfg, in is_config_schedulable() argument
1363 if (display_cfg->display_config.num_streams == 0) { in is_config_schedulable()
1516 const struct display_configuation_with_meta *display_cfg, in stream_matches_drr_policy() argument
1525 display_cfg->display_config.num_streams > 1 && in stream_matches_drr_policy()
1567 const struct display_configuation_with_meta *display_cfg, in validate_pstate_support_strategy_cofunctionality() argument
1589 if (!all_planes_match_method(display_cfg, s->pmo_dcn4.stream_plane_mask[stream_index], in validate_pstate_support_strategy_cofunctionality()
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| H A D | dml2_pmo_dcn3.c | 183 static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int … in count_planes_with_stream_index() argument
188 for (i = 0; i < display_cfg->num_planes; i++) { in count_planes_with_stream_index()
189 if (display_cfg->plane_descriptors[i].stream_index == stream_index) in count_planes_with_stream_index()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 80 const struct display_configuation_with_meta *display_cfg; member
96 const struct display_configuation_with_meta *display_cfg; member
363 const struct display_configuation_with_meta *display_cfg; member
374 struct dml_display_cfg_st *display_cfg; member
394 const struct display_configuation_with_meta *display_cfg; member
732 const struct dml2_display_cfg *display_cfg; member
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| H A D | dml2_top_soc15.c | 250 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
302 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
532 if (!params->display_cfg->plane_descriptors[plane_index].surface.dcc.enable) in dml2_top_mcache_validate_admissability()
535 plane = ¶ms->display_cfg->plane_descriptors[plane_index]; in dml2_top_mcache_validate_admissability()
536 stream = ¶ms->display_cfg->stream_descriptors[plane->stream_index]; in dml2_top_mcache_validate_admissability()
788 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
811 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
843 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
854 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
983 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_util.h | 69 …ML_DLL_EXPORT__ dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg);
70 __DML_DLL_EXPORT__ dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg…
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| H A D | dml2_wrapper.c | 97 const struct dml_display_cfg_st *display_cfg, in pack_and_call_dml_mode_support_ex() argument
103 s->mode_support_params.in_display_cfg = display_cfg; in pack_and_call_dml_mode_support_ex()
305 static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, in are_timings_requiring_odm_doing_blending() argument
311 for (i = 0; i < display_cfg->num_surfaces; i++) in are_timings_requiring_odm_doing_blending()
312 planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; in are_timings_requiring_odm_doing_blending()
322 …figuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, in does_configuration_meet_sw_policies() argument
328 if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) in does_configuration_meet_sw_policies()
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| H A D | display_mode_core.h | 67 const struct dml_display_cfg_st *display_cfg);
72 const struct dml_display_cfg_st *display_cfg,
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| H A D | display_mode_util.c | 728 dml_uint_t dml_get_num_active_planes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_planes() argument
733 if (display_cfg->plane.ViewportWidth[k] > 0) in dml_get_num_active_planes()
743 dml_uint_t dml_get_num_active_pipes(const struct dml_display_cfg_st *display_cfg) in dml_get_num_active_pipes() argument
747 for (dml_uint_t j = 0; j < dml_get_num_active_planes(display_cfg); j++) { in dml_get_num_active_pipes()
748 num_active_pipes = num_active_pipes + display_cfg->hw.DPPPerSurface[j]; in dml_get_num_active_pipes()
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| H A D | display_mode_core.c | 2695 dml_uint_t num_active_planes = dml_get_num_active_planes(display_cfg); in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2699 display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
2701 display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
10065 const struct dml_display_cfg_st *display_cfg) in cache_display_cfg() argument
10067 mode_lib->ms.cache_display_cfg = *display_cfg; in cache_display_cfg()
10093 const struct dml_display_cfg_st *display_cfg) in dml_mode_support() argument
10099 cache_display_cfg(mode_lib, display_cfg); in dml_mode_support()
10125 const struct dml_display_cfg_st *display_cfg, in dml_mode_programming() argument
10141 cache_display_cfg(mode_lib, display_cfg); in dml_mode_programming()
10159 const struct dml_display_cfg_st *display_cfg, in mode_support_pwr_states() argument
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