| /linux-6.15/arch/arm/crypto/ |
| H A D | sha2-ce-core.S | 29 dg1 .req q14
37 sha256h.32 dg0, dg1, tb\ev
38 sha256h2.32 dg1, dg2, tb\ev
95 vmov dg1, dgb
117 vadd.u32 dgb, dgb, dg1
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| H A D | sha1-ce-core.S | 36 .macro add_only, op, ev, rc, s0, dg1 argument
41 .ifb \dg1
44 sha1\op\().32 dg0, \dg1, ta\ev
48 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 argument
50 add_only \op, \ev, \rc, \s1, \dg1
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| /linux-6.15/arch/arm64/crypto/ |
| H A D | sha1-ce-core.S | 34 .macro add_only, op, ev, rc, s0, dg1 argument
38 .ifnb \dg1
39 sha1\op dg0q, \dg1, t0.4s
52 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 argument
54 add_only \op, \ev, \rc, \s1, \dg1
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| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_combo_phy.c | 143 display->platform.dg1) in has_phy_misc()
210 else if (display->platform.dg1 || display->platform.rocketlake) in phy_is_master()
380 if (display->platform.tigerlake || display->platform.dg1) { in icl_combo_phys_uninit()
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| H A D | intel_display_device.h | 85 func(dg1) \
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| H A D | intel_dpll_mgr.c | 207 if (display->platform.dg1) in intel_combo_pll_enable_reg()
3364 } else if (display->platform.dg1) { in icl_get_combo_phy_dpll()
3705 } else if (display->platform.dg1) { in icl_pll_get_hw_state()
3769 } else if (display->platform.dg1) { in icl_dpll_write()
4326 else if (display->platform.dg1) in intel_shared_dpll_init()
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| H A D | intel_display_power.c | 936 else if (display->platform.dg1) in get_allowed_dc_mask()
1597 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
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| H A D | intel_dmc.c | 139 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02)
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| H A D | intel_ddi_buf_trans.c | 1730 } else if (display->platform.dg1) { in intel_ddi_buf_trans_init()
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| H A D | intel_display_power_map.c | 1836 else if (display->platform.dg1) in intel_display_power_map_init()
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| H A D | intel_hotplug_irq.c | 1442 HPD_FUNCS(dg1);
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| H A D | intel_bios.c | 2403 else if (display->platform.dg1 || display->platform.rocketlake) in dvo_port_to_port()
3612 } else if (display->platform.dg1 || display->platform.rocketlake) { in map_aux_ch()
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| H A D | intel_display_device.c | 1045 PLATFORM(dg1),
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| H A D | skl_universal_plane.c | 2763 if (display->platform.dg1 || display->platform.rocketlake || in tgl_plane_has_mc_ccs()
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| H A D | intel_display.c | 1822 else if (display->platform.dg1 || display->platform.rocketlake) in intel_phy_is_combo()
1876 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) in intel_port_to_phy()
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| H A D | intel_dp.c | 608 display->platform.dg1 || display->platform.rocketlake) in intel_dp_set_source_rates()
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| /linux-6.15/drivers/gpu/drm/i915/ |
| H A D | TODO.txt | 4 - For discrete memory manager, merge enough dg1 to be able to refactor it to
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| /linux-6.15/drivers/gpu/drm/xe/ |
| H A D | xe_uc_fw.c | 114 fw_def(DG1, major_ver(i915, guc, dg1, 70, 29, 2)) \
125 fw_def(DG1, no_ver(i915, huc, dg1)) \
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| /linux-6.15/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_uc_fw.c | 99 fw_def(DG1, 0, guc_maj(dg1, 70, 5, 1)) \
120 fw_def(DG1, 0, huc_raw(dg1)) \
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