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Searched refs:dev_priv (Results 1 – 25 of 211) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/soc/
H A Dintel_pch.c47 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
63 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
70 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
77 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
85 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
93 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); in intel_pch_type()
144 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in intel_pch_type()
148 drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) || in intel_pch_type()
155 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && in intel_pch_type()
215 else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) in intel_virt_detect_pch()
[all …]
H A Dintel_pch.h37 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
38 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
39 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
40 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
41 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
42 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
43 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
44 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
49 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) argument
50 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) argument
[all …]
/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Di915_drv.h27 #define IS_I830(dev_priv) (dev_priv && 0) argument
28 #define IS_I845G(dev_priv) (dev_priv && 0) argument
29 #define IS_I85X(dev_priv) (dev_priv && 0) argument
30 #define IS_I865G(dev_priv) (dev_priv && 0) argument
31 #define IS_I915G(dev_priv) (dev_priv && 0) argument
33 #define IS_I945G(dev_priv) (dev_priv && 0) argument
35 #define IS_I965G(dev_priv) (dev_priv && 0) argument
37 #define IS_G45(dev_priv) (dev_priv && 0) argument
38 #define IS_GM45(dev_priv) (dev_priv && 0) argument
39 #define IS_G4X(dev_priv) (dev_priv && 0) argument
[all …]
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_irq.c172 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
209 drm_dbg(&dev_priv->drm, in ivb_parity_work()
222 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
666 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
689 ibx_irq_reset(dev_priv); in ilk_irq_reset()
919 dev_priv->irq_mask = in i915_irq_postinstall()
1044 dev_priv->irq_mask = in i965_irq_postinstall()
1059 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
1150 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) in intel_irq_init()
1285 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled)) in intel_irq_uninstall()
[all …]
H A Di915_driver.c185 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
186 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
187 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
188 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; in intel_detect_preproduction_hw()
189 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
190 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
191 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
192 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; in intel_detect_preproduction_hw()
193 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; in intel_detect_preproduction_hw()
194 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
[all …]
H A Dintel_gvt.c54 if (IS_BROADWELL(dev_priv)) in is_supported_device()
56 if (IS_SKYLAKE(dev_priv)) in is_supported_device()
58 if (IS_KABYLAKE(dev_priv)) in is_supported_device()
60 if (IS_BROXTON(dev_priv)) in is_supported_device()
64 if (IS_COMETLAKE(dev_priv)) in is_supported_device()
129 iter.i915 = dev_priv; in save_initial_hw_state()
152 drm_dbg(&dev_priv->drm, in intel_gvt_init_device()
163 drm_info(&dev_priv->drm, in intel_gvt_init_device()
169 drm_err(&dev_priv->drm, in intel_gvt_init_device()
185 if (dev_priv->gvt) in intel_gvt_clean_device()
[all …]
/linux-6.15/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c443 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
445 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
454 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
463 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); in vmw_device_init()
535 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
939 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
972 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
976 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
981 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
991 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
[all …]
H A Dvmwgfx_irq.c144 vmw_update_seqno(dev_priv); in vmw_seqno_passed()
148 if (!vmw_has_fences(dev_priv) && vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
187 if (dev_priv->cman) { in vmw_fallback_wait()
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_remove()
279 vmw_generic_waiter_add(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_add()
285 vmw_generic_waiter_remove(dev_priv, vmw_irqflag_fence_goal(dev_priv), in vmw_goal_waiter_remove()
341 drm_err(&dev_priv->drm, in vmw_irq_install()
352 drm_err(&dev_priv->drm, in vmw_irq_install()
356 dev_priv->irqs[i] = ret; in vmw_irq_install()
[all …]
H A Dvmwgfx_cmd.c47 if (!dev_priv->has_mob) in vmw_supports_3d()
103 if (!dev_priv->fifo_mem) in vmw_fifo_create()
131 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
144 drm_info(&dev_priv->drm, in vmw_fifo_create()
151 drm_warn(&dev_priv->drm, in vmw_fifo_create()
184 dev_priv->fifo = NULL; in vmw_fifo_destroy()
370 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
474 if (dev_priv->cman) in vmw_cmd_commit()
489 if (dev_priv->cman) in vmw_cmd_commit_flush()
506 if (dev_priv->cman) in vmw_cmd_flush()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_pch_refclk.c34 lpt_fdi_reset_mphy(dev_priv); in lpt_fdi_program_mphy()
112 intel_sbi_lock(dev_priv); in lpt_disable_iclkip()
118 intel_sbi_unlock(dev_priv); in lpt_disable_iclkip()
199 intel_sbi_lock(dev_priv); in lpt_program_iclkip()
240 intel_sbi_lock(dev_priv); in lpt_get_iclkip()
279 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && in lpt_enable_clkout_dp()
283 intel_sbi_lock(dev_priv); in lpt_enable_clkout_dp()
314 intel_sbi_lock(dev_priv); in lpt_disable_clkout_dp()
378 intel_sbi_lock(dev_priv); in lpt_bend_clkout_dp()
427 if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) && in wrpll_uses_pch_ssc()
[all …]
H A Dintel_display_irq.c333 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
357 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
501 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
535 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_pipestat_irq_ack()
1368 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); in gen8_de_irq_handler()
1404 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in gen8_de_irq_handler()
1489 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && in gen8_de_irq_handler()
1979 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
2123 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
2231 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
[all …]
H A Dintel_hotplug.c170 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
174 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
244 drm_info(&dev_priv->drm, in intel_hpd_irq_storm_switch_to_polling()
287 drm_dbg(&dev_priv->drm, in intel_hpd_irq_storm_reenable_work()
572 drm_dbg(&dev_priv->drm, in intel_hpd_irq_handler()
601 drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
644 queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work); in intel_hpd_irq_handler()
670 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_init()
753 drm_WARN_ON(&dev_priv->drm, in i915_hpd_poll_init_work()
858 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_disable()
[all …]
H A Dintel_pipe_crc.c173 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); in vlv_pipe_crc_ctl_reg()
189 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_pipe_crc_ctl_reg()
235 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); in vlv_undo_pipe_scramble_reset()
252 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_undo_pipe_scramble_reset()
290 if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) in intel_crtc_crc_setup_workarounds()
415 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
417 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in get_new_crc_ctl_reg()
545 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
547 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in intel_is_valid_crc_source()
622 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
[all …]
H A Dintel_hotplug_irq.c139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
151 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
163 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) in intel_hpd_init_pins()
172 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) in intel_hpd_init_pins()
174 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) in intel_hpd_init_pins()
189 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask, in i915_hotplug_interrupt_update_locked()
422 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
452 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv))); in i9xx_hpd_irq_ack()
464 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
479 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
[all …]
H A Dintel_pch_display.c129 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_hdmi_port()
148 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_dp_port()
233 intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
235 intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
237 intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
240 intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
242 intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
244 intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
246 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder))); in ilk_pch_transcoder_set_timings()
265 if (HAS_PCH_CPT(dev_priv)) { in ilk_enable_pch_transcoder()
[all …]
H A Di9xx_wm.c154 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in _intel_set_memory_cxsr()
158 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { in _intel_set_memory_cxsr()
171 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { in _intel_set_memory_cxsr()
244 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_set_memory_cxsr()
681 intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv), in pnv_update_wm()
690 intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv), in pnv_update_wm()
2323 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
2337 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) in i9xx_update_wm()
2867 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in ilk_setup_wm_latency()
3164 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in ilk_wm_lp_latency()
[all …]
H A Dintel_wm.c149 drm_dbg_kms(&dev_priv->drm, in intel_print_wm_latency()
164 drm_dbg_kms(&dev_priv->drm, in intel_print_wm_latency()
193 IS_VALLEYVIEW(dev_priv) || in wm_latency_show()
194 IS_CHERRYVIEW(dev_priv) || in wm_latency_show()
195 IS_G4X(dev_priv)) in wm_latency_show()
212 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_show()
227 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_show()
242 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_show()
256 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()
266 if (HAS_GMCH(dev_priv)) in spr_wm_latency_open()
[all …]
H A Dvlv_dsi_pll.c220 vlv_cck_get(dev_priv); in vlv_dsi_pll_enable()
237 vlv_cck_put(dev_priv); in vlv_dsi_pll_enable()
241 vlv_cck_put(dev_priv); in vlv_dsi_pll_enable()
253 vlv_cck_get(dev_priv); in vlv_dsi_pll_disable()
260 vlv_cck_put(dev_priv); in vlv_dsi_pll_disable()
287 drm_dbg(&dev_priv->drm, in bxt_dsi_pll_is_enabled()
293 drm_dbg(&dev_priv->drm, in bxt_dsi_pll_is_enabled()
316 drm_err(&dev_priv->drm, in bxt_dsi_pll_disable()
328 vlv_cck_get(dev_priv); in vlv_dsi_get_pclk()
331 vlv_cck_put(dev_priv); in vlv_dsi_get_pclk()
[all …]
H A Dintel_vrr_regs.h16 #define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) argument
30 #define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) argument
37 #define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) argument
44 #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
54 #define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) argument
74 #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
85 #define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ argument
93 #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) argument
100 #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) argument
105 #define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) argument
[all …]
H A Di9xx_plane_regs.h12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
83 #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) argument
93 #define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) argument
[all …]
/linux-6.15/drivers/gpu/drm/gma500/
H A Dpsb_drv.c157 psb_spank(dev_priv); in psb_do_init()
186 if (dev_priv->mmu) { in psb_driver_unload()
191 (dev_priv->mmu), in psb_driver_unload()
248 pg = &dev_priv->gtt; in psb_driver_load()
252 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
256 dev_priv->vdc_reg = in psb_driver_load()
286 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
289 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
311 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
341 if (!dev_priv->mmu) in psb_driver_load()
[all …]
H A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
84 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
92 dev_priv->edp.lanes = 1; in parse_edp()
95 dev_priv->edp.lanes = 2; in parse_edp()
99 dev_priv->edp.lanes = 4; in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
[all …]
H A Dbacklight.c24 dev_priv->backlight_enabled = true; in gma_backlight_enable()
25 dev_priv->ops->backlight_set(dev, dev_priv->backlight_level); in gma_backlight_enable()
32 dev_priv->backlight_enabled = false; in gma_backlight_disable()
40 dev_priv->backlight_level = v; in gma_backlight_set()
41 if (dev_priv->backlight_enabled) in gma_backlight_set()
50 if (dev_priv->ops->backlight_get) in gma_backlight_get_brightness()
53 return dev_priv->backlight_level; in gma_backlight_get_brightness()
81 dev_priv->backlight_level = 100; in gma_backlight_init()
89 dev_priv->ops->backlight_name); in gma_backlight_init()
98 dev_priv->backlight_device = in gma_backlight_init()
[all …]
H A Dpsb_irq.c50 dev_priv->pipestat[pipe] |= mask; in gma_enable_pipestat()
57 gma_power_end(&dev_priv->dev); in gma_enable_pipestat()
66 dev_priv->pipestat[pipe] &= ~mask; in gma_disable_pipestat()
72 gma_power_end(&dev_priv->dev); in gma_disable_pipestat()
91 spin_lock(&dev_priv->irqmask_lock); in gma_pipe_event_handler()
268 if (dev_priv->ops->hotplug) in gma_irq_preinstall()
301 if (dev_priv->ops->hotplug_enable) in gma_irq_postinstall()
315 dev_priv->use_msi = false; in gma_irq_install()
330 dev_priv->irq_enabled = true; in gma_irq_install()
342 if (!dev_priv->irq_enabled) in gma_irq_uninstall()
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H A Dmid_bios.c54 if (dev_priv->iLVDS_enable) { in mid_get_fuse_settings()
55 dev_priv->is_lvds_on = true; in mid_get_fuse_settings()
56 dev_priv->is_mipi_on = false; in mid_get_fuse_settings()
58 dev_priv->is_mipi_on = true; in mid_get_fuse_settings()
59 dev_priv->is_lvds_on = false; in mid_get_fuse_settings()
74 dev_priv->core_freq = 200; in mid_get_fuse_settings()
77 dev_priv->core_freq = 100; in mid_get_fuse_settings()
80 dev_priv->core_freq = 166; in mid_get_fuse_settings()
85 dev_priv->core_freq = 0; in mid_get_fuse_settings()
109 dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id); in mid_get_pci_revID()
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