| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 109 .dcfclk_mhz = 1434.0,
281 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) in sort_entries_with_same_bw()
324 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; in override_max_clk_values()
365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
445 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
455 entry.dcfclk_mhz = 0; in build_synthetic_soc_states()
493 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || in build_synthetic_soc_states()
503 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
561 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && in build_synthetic_soc_states()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_policy.c | 33 if (entry->dcfclk_mhz > 0) { in get_optimal_ntuple()
102 table->state_array[index].dcfclk_mhz = (int)entry->dcfclk_mhz; in insert_entry_into_table_sorted()
137 if (p->in_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz) in dml2_policy_build_synthetic_soc_states()
138 max_dcfclk_mhz = (int) p->in_states->state_array[i].dcfclk_mhz; in dml2_policy_build_synthetic_soc_states()
178 s->entry.dcfclk_mhz = p->dcfclk_stas_mhz[i]; in dml2_policy_build_synthetic_soc_states()
189 s->entry.dcfclk_mhz = 0; in dml2_policy_build_synthetic_soc_states()
204 s->entry.dcfclk_mhz = 0; in dml2_policy_build_synthetic_soc_states()
213 s->entry.dcfclk_mhz = 0; in dml2_policy_build_synthetic_soc_states()
222 if (p->out_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz || in dml2_policy_build_synthetic_soc_states()
260 p->out_states->state_array[i].dcfclk_mhz = min_dcfclk_mhz; in dml2_policy_build_synthetic_soc_states()
[all …]
|
| H A D | dml2_translation_helper.c | 366 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
388 p->in_states->state_array[1].dcfclk_mhz = 1564.0; in dml2_init_soc_states()
402 p->in_states->state_array[0].dcfclk_mhz = 300.0; in dml2_init_soc_states()
424 p->in_states->state_array[1].dcfclk_mhz = 1434.0; in dml2_init_soc_states()
437 p->in_states->state_array[0].dcfclk_mhz = 200; //300.0; in dml2_init_soc_states()
459 p->in_states->state_array[1].dcfclk_mhz = 1800; //1564.0; in dml2_init_soc_states()
505 p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz; in dml2_init_soc_states()
523 …p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dc… in dml2_init_soc_states()
566 if (p->in_states->state_array[i].dcfclk_mhz > max_dcfclk_mhz) in dml2_init_soc_states()
601 p->out_states->state_array[i].dcfclk_mhz = p->in_states->state_array[i].dcfclk_mhz; in dml2_init_soc_states()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
320 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_fpu_update_bw_bounding_box()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
289 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
303 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
309 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
326 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
327 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 101 .dcfclk_mhz = 400.0,
114 .dcfclk_mhz = 600.0,
127 .dcfclk_mhz = 738.0,
140 .dcfclk_mhz = 800.0,
153 .dcfclk_mhz = 873.0,
166 .dcfclk_mhz = 960.0,
179 .dcfclk_mhz = 1067.0,
192 .dcfclk_mhz = 1200.0,
306 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn351_update_bw_bounding_box_fpu()
308 clock_limits[i].dcfclk_mhz < in dcn351_update_bw_bounding_box_fpu()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 119 .dcfclk_mhz = 400.0,
131 .dcfclk_mhz = 400.0,
143 .dcfclk_mhz = 608.0,
155 .dcfclk_mhz = 676.0,
167 .dcfclk_mhz = 810.0,
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_fpu_update_bw_bounding_box()
351 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_fpu_update_bw_bounding_box()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 226 .dcfclk_mhz = 560.0,
237 .dcfclk_mhz = 694.0,
248 .dcfclk_mhz = 875.0,
337 .dcfclk_mhz = 560.0,
448 .dcfclk_mhz = 560.0,
459 .dcfclk_mhz = 694.0,
470 .dcfclk_mhz = 875.0,
1960 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) in dcn20_cap_soc_clocks()
2219 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
2382 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; in construct_low_pstate_lvl()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
231 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 130 .dcfclk_mhz = 1564.0,
2734 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz) in sort_entries_with_same_bw()
2777 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz; in override_max_clk_values()
2818 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
2819 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
2898 entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
2908 entry.dcfclk_mhz = 0; in build_synthetic_soc_states()
2946 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz || in build_synthetic_soc_states()
2956 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz; in build_synthetic_soc_states()
3012 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && in build_synthetic_soc_states()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 258 if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <= in dcn35_update_bw_bounding_box_fpu()
259 clk_table->entries[i].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
272 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu()
275 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()
277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
278 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
358 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
359 clock_limits[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
629 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
697 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box()
759 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= in dcn316_update_bw_bounding_box()
760 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box()
769 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn316_update_bw_bounding_box()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn401/ |
| H A D | dcn401_fpu.c | 22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
32 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
200 if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz) in dcn401_update_bw_bounding_box_fpu()
201 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz = in dcn401_update_bw_bounding_box_fpu()
202 dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz; in dcn401_update_bw_bounding_box_fpu()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 406 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges()
409 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
506 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn315_clk_mgr_helper_populate_bw_params()
516 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn315_clk_mgr_helper_populate_bw_params()
528 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0]; in dcn315_clk_mgr_helper_populate_bw_params()
548 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params()
549 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
568 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn315_clk_mgr_helper_populate_bw_params()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
497 .dcfclk_mhz = 400,
504 .dcfclk_mhz = 483,
511 .dcfclk_mhz = 602,
518 .dcfclk_mhz = 738,
593 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
598 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCF… in vg_clk_mgr_helper_populate_bw_params()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 477 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
479 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
581 .dcfclk_mhz = 400,
588 .dcfclk_mhz = 483,
595 .dcfclk_mhz = 602,
602 .dcfclk_mhz = 738,
670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 509 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn314_build_watermark_ranges()
512 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
664 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()
675 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn314_clk_mgr_helper_populate_bw_params()
691 …bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK… in dcn314_clk_mgr_helper_populate_bw_params()
720 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
721 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
735 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn314_clk_mgr_helper_populate_bw_params()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 353 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
363 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
379 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
534 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()
570 unsigned int *dcfclk_mhz, in dcn30_fpu_update_bw_bounding_box() argument
582 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
583 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
|
| H A D | dcn30_fpu.h | 60 unsigned int *dcfclk_mhz,
|
| /linux-6.15/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 764 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn35_build_watermark_ranges()
767 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn35_build_watermark_ranges()
961 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn35_clk_mgr_helper_populate_bw_params()
971 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; in dcn35_clk_mgr_helper_populate_bw_params()
990 bw_params->clk_table.entries[i].dcfclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1032 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1033 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1049 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); in dcn35_clk_mgr_helper_populate_bw_params()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 159 double dcfclk_mhz; member
553 double dcfclk_mhz; member
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 143 .dcfclk_mhz = 1000.0,
154 .dcfclk_mhz = 1000.0,
165 .dcfclk_mhz = 1000.0,
176 .dcfclk_mhz = 1000.0,
188 .dcfclk_mhz = 1000.0,
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2105 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2128 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2129 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2166 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()
2167 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2198 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2202 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2211 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2217 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2223 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_translation_helper.c | 103 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && in dml21_apply_soc_bb_overrides()
104 dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { in dml21_apply_soc_bb_overrides()
105 … if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { in dml21_apply_soc_bb_overrides()
106 dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
113 dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; in dml21_apply_soc_bb_overrides()
|