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Searched refs:dccg_mask (Results 1 – 25 of 37) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
H A Ddcn30_dccg.c38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
59 const struct dccg_mask *dccg_mask) in dccg3_create() argument
75 dccg_dcn->dccg_mask = dccg_mask; in dccg3_create()
84 const struct dccg_mask *dccg_mask) in dccg30_create() argument
100 dccg_dcn->dccg_mask = dccg_mask; in dccg30_create()
H A Ddcn30_dccg.h58 const struct dccg_mask *dccg_mask);
64 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.c38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
58 const struct dccg_mask *dccg_mask) in dccg301_create() argument
74 dccg_dcn->dccg_mask = dccg_mask; in dccg301_create()
H A Ddcn301_dccg.h57 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
H A Ddcn201_dccg.c39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
66 const struct dccg_mask *dccg_mask) in dccg201_create() argument
82 dccg_dcn->dccg_mask = dccg_mask; in dccg201_create()
H A Ddcn201_dccg.h35 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
H A Ddcn21_dccg.c39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
113 const struct dccg_mask *dccg_mask) in dccg21_create() argument
129 dccg_dcn->dccg_mask = dccg_mask; in dccg21_create()
H A Ddcn21_dccg.h33 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
149 const struct dccg_mask *dccg_mask) in dccg2_create() argument
165 dccg_dcn->dccg_mask = dccg_mask; in dccg2_create()
H A Ddcn20_dccg.h372 struct dccg_mask { struct
437 const struct dccg_mask *dccg_mask; member
460 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
356 const struct dccg_mask *dccg_mask) in dccg32_create() argument
372 dccg_dcn->dccg_mask = dccg_mask; in dccg32_create()
H A Ddcn32_dccg.h123 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
387 const struct dccg_mask *dccg_mask) in dccg314_create() argument
403 dccg_dcn->dccg_mask = dccg_mask; in dccg314_create()
H A Ddcn314_dccg.h204 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
736 const struct dccg_mask *dccg_mask) in dccg31_create() argument
752 dccg_dcn->dccg_mask = dccg_mask; in dccg31_create()
H A Ddcn31_dccg.h166 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c48 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
895 const struct dccg_mask *dccg_mask) in dccg401_create() argument
911 dccg_dcn->dccg_mask = dccg_mask; in dccg401_create()
H A Ddcn401_dccg.h242 const struct dccg_mask *dccg_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.h239 const struct dccg_mask *dccg_mask);
H A Ddcn35_dccg.c38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
2413 const struct dccg_mask *dccg_mask) in dccg35_create() argument
2433 dccg_dcn->dccg_mask = dccg_mask; in dccg35_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c558 static const struct dccg_mask dccg_mask = { variable
1188 pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn201_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c1119 static const struct dccg_mask dccg_mask = { variable
1276 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn303_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c1174 static const struct dccg_mask dccg_mask = { variable
1343 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn302_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c593 static const struct dccg_mask dccg_mask = { variable
1548 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn301_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c232 static const struct dccg_mask dccg_mask = { variable
1510 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); in dcn21_resource_construct()

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