Searched refs:dc_mode_limit (Results 1 – 7 of 7) sorted by relevance
103 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && in dml21_apply_soc_bb_overrides()104 dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { in dml21_apply_soc_bb_overrides()126 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && in dml21_apply_soc_bb_overrides()127 dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { in dml21_apply_soc_bb_overrides()149 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && in dml21_apply_soc_bb_overrides()150 dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { in dml21_apply_soc_bb_overrides()172 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && in dml21_apply_soc_bb_overrides()195 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && in dml21_apply_soc_bb_overrides()196 dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { in dml21_apply_soc_bb_overrides()218 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz && in dml21_apply_soc_bb_overrides()[all …]
257 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks()259 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0; in dcn401_init_clocks()266 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz == in dcn401_init_clocks()268 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0; in dcn401_init_clocks()276 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz == in dcn401_init_clocks()278 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0; in dcn401_init_clocks()286 …if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz … in dcn401_init_clocks()288 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0; in dcn401_init_clocks()1386 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0; in dcn401_get_memclk_states_from_smu()1393 if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz == in dcn401_get_memclk_states_from_smu()[all …]
194 …clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()200 …clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()207 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = in dcn32_init_clocks()218 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950) in dcn32_init_clocks()219 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950; in dcn32_init_clocks()226 …clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_init_clocks()228 if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950) in dcn32_init_clocks()229 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950; in dcn32_init_clocks()1039 …clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PP… in dcn32_get_memclk_states_from_smu()1040 …clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mh… in dcn32_get_memclk_states_from_smu()[all …]
382 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()387 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()392 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()399 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); in build_synthetic_soc_states()
258 struct clk_limit_table_entry dc_mode_limit; member
147 …table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dcfclk_mhz) || in dcn401_init_hw()148 …ble.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dispclk_mhz) || in dcn401_init_hw()149 …table.num_entries_per_clk.num_dtbclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.dtbclk_mhz) || in dcn401_init_hw()150 …clk_table.num_entries_per_clk.num_fclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.fclk_mhz) || in dcn401_init_hw()151 …table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.memclk_mhz) || in dcn401_init_hw()152 …k_table.num_entries_per_clk.num_socclk_levels && dc->clk_mgr->bw_params->dc_mode_limit.socclk_mhz); in dcn401_init_hw()
2835 if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz) in build_synthetic_soc_states()2840 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()2845 if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz) in build_synthetic_soc_states()2852 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data); in build_synthetic_soc_states()