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Searched refs:cw6 (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c127 const struct dmub_window *cw6, in dmub_dcn30_setup_windows() argument
194 offset = cw6->offset; in dmub_dcn30_setup_windows()
198 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn30_setup_windows()
200 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn30_setup_windows()
H A Ddmub_dcn30.h46 const struct dmub_window *cw6,
H A Ddmub_dcn20.c194 const struct dmub_window *cw6, in dmub_dcn20_setup_windows() argument
264 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
268 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn20_setup_windows()
270 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn20_setup_windows()
H A Ddmub_dcn31.c195 const struct dmub_window *cw6, in dmub_dcn31_setup_windows() argument
234 offset = cw6->offset; in dmub_dcn31_setup_windows()
238 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn31_setup_windows()
240 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn31_setup_windows()
H A Ddmub_dcn32.c219 const struct dmub_window *cw6, in dmub_dcn32_setup_windows() argument
258 offset = cw6->offset; in dmub_dcn32_setup_windows()
262 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn32_setup_windows()
264 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn32_setup_windows()
H A Ddmub_dcn35.c232 const struct dmub_window *cw6, in dmub_dcn35_setup_windows() argument
271 offset = cw6->offset; in dmub_dcn35_setup_windows()
275 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn35_setup_windows()
277 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn35_setup_windows()
H A Ddmub_dcn401.c206 const struct dmub_window *cw6, in dmub_dcn401_setup_windows() argument
245 offset = cw6->offset; in dmub_dcn401_setup_windows()
249 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn401_setup_windows()
251 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn401_setup_windows()
H A Ddmub_srv.c628 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; in dmub_srv_hw_init() local
707 cw6.offset.quad_part = fw_state_fb->gpu_addr; in dmub_srv_hw_init()
708 cw6.region.base = DMUB_CW6_BASE; in dmub_srv_hw_init()
709 cw6.region.top = cw6.region.base + fw_state_fb->size; in dmub_srv_hw_init()
722 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6); in dmub_srv_hw_init()
H A Ddmub_dcn20.h200 const struct dmub_window *cw6,
H A Ddmub_dcn31.h202 const struct dmub_window *cw6,
H A Ddmub_dcn32.h209 const struct dmub_window *cw6,
H A Ddmub_dcn35.h222 const struct dmub_window *cw6,
H A Ddmub_dcn401.h219 const struct dmub_window *cw6,
/linux-6.15/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h397 const struct dmub_window *cw6,