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Searched refs:csr_write (Results 1 – 24 of 24) sorted by relevance

/linux-6.15/arch/riscv/kvm/
H A Dmain.c31 csr_write(CSR_HEDELEG, KVM_HEDELEG_DEFAULT); in kvm_arch_enable_virtualization_cpu()
32 csr_write(CSR_HIDELEG, KVM_HIDELEG_DEFAULT); in kvm_arch_enable_virtualization_cpu()
35 csr_write(CSR_HCOUNTEREN, 0x02); in kvm_arch_enable_virtualization_cpu()
37 csr_write(CSR_HVIP, 0); in kvm_arch_enable_virtualization_cpu()
54 csr_write(CSR_VSIE, 0); in kvm_arch_disable_virtualization_cpu()
55 csr_write(CSR_HVIP, 0); in kvm_arch_disable_virtualization_cpu()
56 csr_write(CSR_HEDELEG, 0); in kvm_arch_disable_virtualization_cpu()
57 csr_write(CSR_HIDELEG, 0); in kvm_arch_disable_virtualization_cpu()
H A Daia.c158 csr_write(CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
161 csr_write(CSR_VSIEH, csr->vsieh); in kvm_riscv_vcpu_aia_load()
162 csr_write(CSR_HVIPH, csr->hviph); in kvm_riscv_vcpu_aia_load()
578 csr_write(CSR_HVIPRIO1, 0x0); in kvm_riscv_aia_enable()
579 csr_write(CSR_HVIPRIO2, 0x0); in kvm_riscv_aia_enable()
581 csr_write(CSR_HVIPH, 0x0); in kvm_riscv_aia_enable()
582 csr_write(CSR_HIDELEGH, 0x0); in kvm_riscv_aia_enable()
583 csr_write(CSR_HVIPRIO1H, 0x0); in kvm_riscv_aia_enable()
584 csr_write(CSR_HVIPRIO2H, 0x0); in kvm_riscv_aia_enable()
658 csr_write(CSR_HGEIE, -1UL); in kvm_riscv_aia_init()
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H A Dvcpu_exit.c121 csr_write(CSR_STVEC, old_stvec); in kvm_riscv_vcpu_unpriv_read()
122 csr_write(CSR_HSTATUS, old_hstatus); in kvm_riscv_vcpu_unpriv_read()
154 csr_write(CSR_VSSTATUS, vsstatus); in kvm_riscv_vcpu_trap_redirect()
157 csr_write(CSR_VSCAUSE, trap->scause); in kvm_riscv_vcpu_trap_redirect()
158 csr_write(CSR_VSTVAL, trap->stval); in kvm_riscv_vcpu_trap_redirect()
159 csr_write(CSR_VSEPC, trap->sepc); in kvm_riscv_vcpu_trap_redirect()
H A Daia_imsic.c64 csr_write(CSR_VSISELECT, __c); \
104 csr_write(CSR_VSISELECT, __c); \
143 csr_write(CSR_VSISELECT, __c); \
144 csr_write(CSR_VSIREG, __v); \
180 csr_write(CSR_VSISELECT, __c); \
383 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_read()
417 csr_write(CSR_HSTATUS, old_hstatus); in imsic_vsfile_local_read()
455 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_rw()
485 csr_write(CSR_HSTATUS, old_hstatus); in imsic_vsfile_local_rw()
532 csr_write(CSR_HSTATUS, new_hstatus); in imsic_vsfile_local_clear()
[all …]
H A Dvcpu.c607 csr_write(CSR_VSSTATUS, csr->vsstatus); in kvm_arch_vcpu_load()
608 csr_write(CSR_VSIE, csr->vsie); in kvm_arch_vcpu_load()
609 csr_write(CSR_VSTVEC, csr->vstvec); in kvm_arch_vcpu_load()
610 csr_write(CSR_VSSCRATCH, csr->vsscratch); in kvm_arch_vcpu_load()
611 csr_write(CSR_VSEPC, csr->vsepc); in kvm_arch_vcpu_load()
612 csr_write(CSR_VSCAUSE, csr->vscause); in kvm_arch_vcpu_load()
613 csr_write(CSR_VSTVAL, csr->vstval); in kvm_arch_vcpu_load()
614 csr_write(CSR_HEDELEG, cfg->hedeleg); in kvm_arch_vcpu_load()
615 csr_write(CSR_HVIP, csr->hvip); in kvm_arch_vcpu_load()
616 csr_write(CSR_VSATP, csr->vsatp); in kvm_arch_vcpu_load()
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H A Dvmid.c29 csr_write(CSR_HGATP, old | HGATP_VMID); in kvm_riscv_gstage_vmid_detect()
33 csr_write(CSR_HGATP, old); in kvm_riscv_gstage_vmid_detect()
H A Dtlb.c105 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_asid_gva()
117 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_asid_all()
145 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_gva()
156 csr_write(CSR_HGATP, hgatp); in kvm_riscv_local_hfence_vvma_all()
H A Dmmu.c744 csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT); in kvm_riscv_gstage_mode_detect()
752 csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT); in kvm_riscv_gstage_mode_detect()
759 csr_write(CSR_HGATP, 0); in kvm_riscv_gstage_mode_detect()
/linux-6.15/arch/riscv/kernel/
H A Dsuspend.c46 csr_write(CSR_SCRATCH, 0); in suspend_restore_csrs()
48 csr_write(CSR_ENVCFG, context->envcfg); in suspend_restore_csrs()
49 csr_write(CSR_TVEC, context->tvec); in suspend_restore_csrs()
50 csr_write(CSR_IE, context->ie); in suspend_restore_csrs()
54 csr_write(CSR_STIMECMP, context->stimecmp); in suspend_restore_csrs()
56 csr_write(CSR_STIMECMPH, context->stimecmph); in suspend_restore_csrs()
60 csr_write(CSR_SATP, context->satp); in suspend_restore_csrs()
H A Dprocess.c126 csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32); in compat_mode_detect()
130 csr_write(CSR_STATUS, tmp); in compat_mode_detect()
/linux-6.15/drivers/clocksource/
H A Dtimer-riscv.c38 csr_write(CSR_STIMECMP, ULONG_MAX); in riscv_clock_event_stop()
40 csr_write(CSR_STIMECMPH, ULONG_MAX); in riscv_clock_event_stop()
53 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); in riscv_clock_next_event()
54 csr_write(CSR_STIMECMPH, next_tval >> 32); in riscv_clock_next_event()
56 csr_write(CSR_STIMECMP, next_tval); in riscv_clock_next_event()
/linux-6.15/arch/riscv/include/asm/
H A Dvector.h154 csr_write(CSR_STATUS, status); in __vstate_csr_save()
180 csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK); in __vstate_csr_restore()
181 csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK); in __vstate_csr_restore()
184 csr_write(CSR_STATUS, status); in __vstate_csr_restore()
186 csr_write(CSR_VCSR, src->vcsr); in __vstate_csr_restore()
H A Dswitch_to.h81 csr_write(CSR_ENVCFG, envcfg); in envcfg_update_bits()
H A Dkvm_nacl.h226 csr_write(__csr, __val); \
H A Dcsr.h536 #define csr_write(csr, val) \ macro
/linux-6.15/arch/riscv/mm/
H A Dcontext.c192 csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | in set_mm_asid()
203 csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode); in set_mm_noasid()
234 csr_write(CSR_SATP, asid_bits); in asids_init()
237 csr_write(CSR_SATP, old); in asids_init()
H A Dkasan_init.c489 csr_write(CSR_SATP, PFN_DOWN(__pa(tmp_pg_dir)) | satp_mode); in kasan_init()
534 csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | satp_mode); in kasan_init()
H A Dinit.c893 csr_write(CSR_SATP, identity_satp); in set_satp_mode()
1363 csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | satp_mode); in setup_vm_final()
/linux-6.15/drivers/cache/
H A Dax45mp_cache.c74 csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start); in ax45mp_cpu_cache_operation()
75 csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op); in ax45mp_cpu_cache_operation()
/linux-6.15/drivers/irqchip/
H A Dirq-riscv-imsic-state.c31 csr_write(CSR_ISELECT, reg); in imsic_csr_write()
32 csr_write(CSR_IREG, val); in imsic_csr_write()
37 csr_write(CSR_ISELECT, reg); in imsic_csr_read()
43 csr_write(CSR_ISELECT, reg); in imsic_csr_read_clear()
49 csr_write(CSR_ISELECT, reg); in imsic_csr_set()
55 csr_write(CSR_ISELECT, reg); in imsic_csr_clear()
/linux-6.15/tools/testing/selftests/kvm/include/riscv/
H A Darch_timer.h32 csr_write(CSR_STIMECMP, cval); in timer_set_cmp()
/linux-6.15/drivers/firmware/efi/libstub/
H A Driscv.c96 csr_write(CSR_SATP, 0); in efi_enter_kernel()
/linux-6.15/drivers/perf/
H A Driscv_pmu_sbi.c698 csr_write(CSR_SCOUNTEREN, in pmu_sbi_set_scounteren()
707 csr_write(CSR_SCOUNTEREN, in pmu_sbi_reset_scounteren()
1068 csr_write(CSR_SCOUNTEREN, 0x7); in pmu_sbi_starting_cpu()
1070 csr_write(CSR_SCOUNTEREN, 0x2); in pmu_sbi_starting_cpu()
1094 csr_write(CSR_SCOUNTEREN, 0x0); in pmu_sbi_dying_cpu()
1295 csr_write(CSR_SCOUNTEREN, 0x7); in riscv_pmu_update_counter_access()
1297 csr_write(CSR_SCOUNTEREN, 0x2); in riscv_pmu_update_counter_access()
/linux-6.15/tools/arch/riscv/include/asm/
H A Dcsr.h497 #define csr_write(csr, val) \ macro