| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_vrr.c | 142 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; in intel_vrr_vblank_exit_length()
170 return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
175 return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
220 crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); in cmrr_get_vtotal()
270 crtc_state->vrr.flipline = crtc_state->vrr.vmin; in intel_vrr_compute_config()
296 crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); in intel_vrr_compute_config()
297 crtc_state->vrr.vmin = crtc_state->vrr.vmax; in intel_vrr_compute_config()
298 crtc_state->vrr.flipline = crtc_state->vrr.vmin; in intel_vrr_compute_config()
333 crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state); in intel_vrr_compute_config_late()
334 crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state); in intel_vrr_compute_config_late()
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| H A D | intel_color.c | 435 (crtc_state->hw.degamma_lut || crtc_state->hw.ctm); in ilk_lut_limited_range()
702 vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc); in vlv_assign_csc()
2391 crtc_state->wgc_enable = crtc_state->hw.ctm; in vlv_color_check()
2457 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
2586 crtc_state->csc_enable = ilk_csc_enable(crtc_state); in ilk_color_check()
2588 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
2590 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
2700 crtc_state->csc_enable = ilk_csc_enable(crtc_state); in ivb_color_check()
2702 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
2704 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
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| H A D | intel_atomic.c | 243 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
244 if (!crtc_state) in intel_crtc_duplicate_state()
252 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
254 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
257 if (crtc_state->pre_csc_lut) in intel_crtc_duplicate_state()
259 if (crtc_state->post_csc_lut) in intel_crtc_duplicate_state()
276 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
280 crtc_state->use_dsb = false; in intel_crtc_duplicate_state()
282 return &crtc_state->uapi; in intel_crtc_duplicate_state()
321 kfree(crtc_state); in intel_crtc_destroy_state()
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| H A D | intel_modeset_setup.c | 48 if (!crtc_state->hw.active) in intel_crtc_disable_noatomic_begin()
328 crtc_state->uapi.enable = crtc_state->hw.enable; in intel_crtc_copy_hw_to_uapi_state()
329 crtc_state->uapi.active = crtc_state->hw.active; in intel_crtc_copy_hw_to_uapi_state()
331 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0); in intel_crtc_copy_hw_to_uapi_state()
333 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; in intel_crtc_copy_hw_to_uapi_state()
334 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; in intel_crtc_copy_hw_to_uapi_state()
592 crtc_state->hw.active; in intel_sanitize_encoder()
594 if (crtc_state && has_bogus_dpll_config(crtc_state)) { in intel_sanitize_encoder()
617 if (crtc_state) { in intel_sanitize_encoder()
714 crtc_state->hw.enable = crtc_state->hw.active; in intel_modeset_readout_hw_state()
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| H A D | intel_dpll.c | 1406 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1413 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1505 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1532 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1577 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1580 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1618 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1621 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1657 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1660 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
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| H A D | intel_pfit.c | 23 &crtc_state->hw.adjusted_mode; in intel_pch_pfit_check_dst_window()
147 &crtc_state->hw.adjusted_mode; in intel_pch_pfit_check_timings()
172 if (crtc_state->uapi.encoder_mask && in intel_pch_pfit_check_cloning()
189 &crtc_state->hw.adjusted_mode; in pch_panel_fitting()
253 crtc_state->pch_pfit.enabled = true; in pch_panel_fitting()
345 &crtc_state->hw.adjusted_mode; in i965_scale_aspect()
423 &crtc_state->hw.adjusted_mode; in intel_gmch_pfit_check_timings()
571 if (!crtc_state->pch_pfit.enabled) in ilk_pfit_enable()
624 crtc_state->pch_pfit.enabled = true; in ilk_pfit_get_config()
648 if (!crtc_state->gmch_pfit.control) in i9xx_pfit_enable()
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| H A D | intel_ddi.c | 2678 crtc_state); in mtl_ddi_pre_enable_dp()
2840 crtc_state); in tgl_ddi_pre_enable_dp()
2931 crtc_state); in hsw_ddi_pre_enable_dp()
2955 crtc_state); in intel_ddi_pre_enable_dp()
3354 crtc_state); in trans_port_sync_stop_link_train()
3898 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3900 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
4377 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || in intel_ddi_sync_state()
4533 crtc_state)) in intel_ddi_port_sync_transcoders()
4551 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
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| H A D | intel_vdsc.c | 382 return crtc_state->dsc.num_streams; in intel_dsc_get_vdsc_per_pipe()
751 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { in intel_uncompressed_joiner_enable()
773 intel_dsc_pps_configure(crtc_state); in intel_dsc_enable()
786 if (crtc_state->joiner_pipes) { in intel_dsc_enable()
985 crtc_state->dsc.num_streams = 3; in intel_dsc_get_config()
987 crtc_state->dsc.num_streams = 2; in intel_dsc_get_config()
989 crtc_state->dsc.num_streams = 1; in intel_dsc_get_config()
991 intel_dsc_get_pps_config(crtc_state); in intel_dsc_get_config()
1002 crtc_state->dsc.slice_count, in intel_vdsc_dump_state()
1003 crtc_state->dsc.num_streams); in intel_vdsc_dump_state()
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| H A D | hsw_ips.c | 23 if (!crtc_state->ips_enabled) in hsw_ips_enable()
71 if (!crtc_state->ips_enabled) in hsw_ips_disable()
205 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
243 crtc_state->ips_enabled = false; in hsw_ips_compute_config()
254 if (crtc_state->crc_enabled) in hsw_ips_compute_config()
273 crtc_state->ips_enabled = true; in hsw_ips_compute_config()
294 crtc_state->ips_enabled = true; in hsw_ips_get_config()
312 struct intel_crtc_state *crtc_state; in hsw_ips_debugfs_false_color_set() local
323 if (!crtc_state->hw.active) in hsw_ips_debugfs_false_color_set()
326 if (crtc_state->uapi.commit && in hsw_ips_debugfs_false_color_set()
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| H A D | intel_ddi_buf_trans.c | 1306 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1360 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1385 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1463 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1476 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1507 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1550 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1561 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
1589 if (crtc_state->port_clock > 270000) in adlp_get_combo_buf_trans_dp()
1683 intel_dp_is_uhbr(crtc_state)) in dg2_get_snps_buf_trans()
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| H A D | intel_crtc.c | 166 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_state_alloc()
168 if (crtc_state) in intel_crtc_state_alloc()
171 return crtc_state; in intel_crtc_state_alloc()
177 memset(crtc_state, 0, sizeof(*crtc_state)); in intel_crtc_state_reset()
199 if (!crtc_state) { in intel_crtc_alloc()
205 crtc->config = crtc_state; in intel_crtc_alloc()
422 !crtc_state->preload_luts && in intel_crtc_needs_vblank_work()
426 !crtc_state->use_dsb; in intel_crtc_needs_vblank_work()
440 if (crtc_state->uapi.event) { in intel_crtc_vblank_work()
619 if (!crtc_state->uapi.event) in intel_crtc_arm_vblank_event()
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| H A D | intel_ddi.h | 27 const struct intel_crtc_state *crtc_state);
30 const struct intel_crtc_state *crtc_state);
32 const struct intel_crtc_state *crtc_state);
39 const struct intel_crtc_state *crtc_state);
42 struct intel_crtc_state *crtc_state,
45 const struct intel_crtc_state *crtc_state);
50 const struct intel_crtc_state *crtc_state);
52 struct intel_crtc_state *crtc_state);
55 const struct intel_crtc_state *crtc_state);
69 const struct intel_crtc_state *crtc_state,
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| H A D | intel_vrr.h | 19 bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
21 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
23 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
25 void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
27 const struct intel_crtc_state *crtc_state);
29 const struct intel_crtc_state *crtc_state);
30 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
32 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
33 int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state);
34 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
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| H A D | intel_dp_link_training.c | 448 if (intel_dp_is_uhbr(crtc_state)) in intel_dp_get_lane_adjust_train()
491 crtc_state->lane_count, in intel_dp_get_adjust_train()
498 crtc_state->lane_count, in intel_dp_get_adjust_train()
603 crtc_state->lane_count, in intel_dp_set_signal_levels()
610 crtc_state->lane_count, in intel_dp_set_signal_levels()
715 crtc_state->port_clock, crtc_state->vrr.flipline); in intel_dp_update_downspread_ctrl()
1045 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
1144 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
1174 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); in reduce_link_params_in_bw_order()
1291 crtc_state->lane_count, crtc_state->port_clock, in intel_dp_get_link_train_fallback_values()
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| H A D | intel_pch_display.c | 355 ilk_fdi_pll_enable(crtc_state); in ilk_pch_pre_enable()
391 if (crtc_state->shared_dpll == in ilk_pch_enable()
424 &crtc_state->hw.adjusted_mode; in ilk_pch_enable()
486 i9xx_crtc_clock_get(crtc_state); in ilk_pch_clock_get()
495 &crtc_state->fdi_m_n); in ilk_pch_clock_get()
519 &crtc_state->fdi_m_n); in ilk_pch_get_config()
536 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
543 crtc_state->pixel_multiplier = in ilk_pch_get_config()
547 ilk_pch_clock_get(crtc_state); in ilk_pch_get_config()
606 lpt_program_iclkip(crtc_state); in lpt_pch_enable()
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| H A D | intel_display.c | 2427 return intel_vrr_possible(crtc_state) && crtc_state->has_psr && in intel_crtc_needs_wa_14015401596()
2911 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
4179 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4181 crtc_state->linetime = hsw_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
4190 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, in hsw_compute_linetime_wm()
4434 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state_modeset()
4435 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state_modeset()
4558 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); in intel_crtc_prepare_cleared_state()
4701 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && in intel_modeset_pipe_config()
4706 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); in intel_modeset_pipe_config()
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| H A D | intel_audio.c | 203 &crtc_state->hw.adjusted_mode; in audio_config_hdmi_pixel_clock()
235 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
455 lanes = crtc_state->lane_count; in calc_hblank_early_prog()
493 lanes = crtc_state->lane_count; in calc_samples_room()
703 &crtc_state->hw.adjusted_mode; in intel_audio_compute_config()
715 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); in intel_audio_compute_config()
744 if (!crtc_state->has_audio) in intel_audio_codec_enable()
756 crtc_state, in intel_audio_codec_enable()
779 crtc_state->port_clock, in intel_audio_codec_enable()
861 if (!crtc_state->has_audio) in intel_audio_codec_get_config()
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| H A D | intel_psr.c | 1697 crtc_state, in intel_psr_compute_config()
1700 crtc_state->has_psr = crtc_state->has_panel_replay ? true : in intel_psr_compute_config()
1703 if (!crtc_state->has_psr) in intel_psr_compute_config()
1706 crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
2310 if (crtc_state->has_psr) in intel_psr_trigger_frame_change_event()
2488 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
2490 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / in intel_psr2_sel_fetch_pipe_alignment()
2638 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2861 if (!crtc_state->has_psr) in intel_psr_post_plane_update()
3594 if (!crtc_state->has_psr) in intel_psr_lock()
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| H A D | intel_alpm.c | 142 const struct intel_crtc_state *crtc_state) in _lnl_compute_aux_less_alpm_params() argument
249 &crtc_state->hw.adjusted_mode, io_wake_time); in intel_alpm_compute_params()
251 &crtc_state->hw.adjusted_mode, fast_wake_time); in intel_alpm_compute_params()
271 struct intel_crtc_state *crtc_state, in intel_alpm_lobf_compute_config() argument
288 if (crtc_state->has_psr) in intel_alpm_lobf_compute_config()
356 if (crtc_state->has_lobf) in lnl_alpm_configure()
365 const struct intel_crtc_state *crtc_state) in intel_alpm_configure() argument
367 lnl_alpm_configure(intel_dp, crtc_state); in intel_alpm_configure()
375 struct intel_crtc_state *crtc_state; in i915_edp_lobf_info_show() local
390 crtc_state = to_intel_crtc_state(crtc->state); in i915_edp_lobf_info_show()
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| H A D | intel_color.h | 25 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
26 bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
27 void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
29 const struct intel_crtc_state *crtc_state);
31 const struct intel_crtc_state *crtc_state);
32 void intel_color_post_update(const struct intel_crtc_state *crtc_state);
33 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
34 void intel_color_modeset(const struct intel_crtc_state *crtc_state);
35 void intel_color_get_config(struct intel_crtc_state *crtc_state);
36 bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
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| H A D | intel_hdmi.c | 716 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
720 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
775 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
840 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
1040 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
2109 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); in hdmi_bpc_possible()
2164 crtc_state->port_clock = in intel_hdmi_compute_clock()
2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2258 crtc_state->sink_format = in intel_hdmi_compute_output_format()
2267 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
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| H A D | skl_scaler.c | 144 &crtc_state->scaler_state; in skl_update_scaler()
147 &crtc_state->hw.adjusted_mode; in skl_update_scaler()
254 if (crtc_state->pch_pfit.enabled) { in skl_update_scaler_crtc()
261 return skl_update_scaler(crtc_state, !crtc_state->hw.active, in skl_update_scaler_crtc()
267 crtc_state->pch_pfit.enabled); in skl_update_scaler_crtc()
503 &crtc_state->scaler_state; in setup_crtc_scaler()
519 &crtc_state->scaler_state; in setup_plane_scaler()
569 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
729 &crtc_state->scaler_state; in skl_pfit_enable()
742 if (!crtc_state->pch_pfit.enabled) in skl_pfit_enable()
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| H A D | intel_vdsc.h | 18 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
19 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
20 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
21 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
23 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
27 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
29 const struct intel_crtc_state *crtc_state);
31 const struct intel_crtc_state *crtc_state);
33 const struct intel_crtc_state *crtc_state);
34 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
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| H A D | intel_dp_mst.c | 268 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state); in intel_dp_mtp_tu_compute_config()
308 &crtc_state->dp_m_n); in intel_dp_mtp_tu_compute_config()
363 crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu, in intel_dp_mtp_tu_compute_config()
604 crtc_state, in mst_stream_compute_config_limits()
944 if (IS_ERR(crtc_state)) { in mst_connector_atomic_topology_check()
1162 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1168 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
1250 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state)) in enable_bs_jitter_was()
1260 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state)) in enable_bs_jitter_was()
1931 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; in intel_dp_mst_is_master_trans()
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| /linux-6.15/drivers/gpu/drm/vkms/ |
| H A D | vkms_composer.c | 120 if (!crtc_state->gamma_lut.base) in apply_lut()
123 if (!crtc_state->gamma_lut.lut_length) in apply_lut()
369 struct vkms_crtc_state *crtc_state, in blend() argument
506 frame_end = crtc_state->frame_end; in vkms_composer_worker()
508 wb_pending = crtc_state->wb_pending; in vkms_composer_worker()
509 crtc_state->frame_start = 0; in vkms_composer_worker()
510 crtc_state->frame_end = 0; in vkms_composer_worker()
511 crtc_state->crc_pending = false; in vkms_composer_worker()
518 crtc_state->gamma_lut.lut_length = in vkms_composer_worker()
525 crtc_state->gamma_lut.base = NULL; in vkms_composer_worker()
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