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Searched refs:crtc_offsets (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/radeon/
H A Drv515.c46 static const u32 crtc_offsets[2] = { variable
283 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
301 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
303 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
336 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop()
339 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop()
386 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
389 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume()
397 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume()
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H A Devergreen.c123 static const u32 crtc_offsets[6] = variable
2722 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2747 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2750 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
4476 WREG32(INT_MASK + crtc_offsets[i], 0); in evergreen_disable_interrupt_state()
4478 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state()
4576 rdev, INT_MASK + crtc_offsets[i], in evergreen_irq_set()
4599 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_set()
4629 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in evergreen_irq_ack()
4635 WREG32(VBLANK_STATUS + crtc_offsets[j], in evergreen_irq_ack()
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H A Drs600.c57 static const u32 crtc_offsets[2] = { variable
64 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
74 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
75 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
98 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
H A Dsi.c141 static const u32 crtc_offsets[] = { variable
5945 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5947 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
6099 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, in si_irq_set()
6105 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set()
6137 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); in si_irq_ack()
6144 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in si_irq_ack()
6150 WREG32(VBLANK_STATUS + crtc_offsets[j], in si_irq_ack()
6153 WREG32(VLINE_STATUS + crtc_offsets[j], in si_irq_ack()
H A Dr600.c103 static const u32 crtc_offsets[2] = { variable
1593 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1594 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1602 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c57 static const u32 crtc_offsets[] = { variable
420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
494 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_disable_dce()
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce()
498 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_disable_dce()
3162 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state()
3165 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state()
3251 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack()
3264 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack()
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H A Ddce_v11_0.c57 static const u32 crtc_offsets[] = variable
442 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
526 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_disable_dce()
527 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
529 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_disable_dce()
530 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_disable_dce()
3293 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state()
3296 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state()
3382 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v11_0_crtc_vblank_int_ack()
3395 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vline_int_ack()
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H A Ddce_v8_0.c57 static const u32 crtc_offsets[6] = { variable
153 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v8_0_vblank_get_counter()
213 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
381 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
452 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_disable_dce()
453 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce()
455 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_disable_dce()
456 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_disable_dce()
3153 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v8_0_set_pageflip_interrupt_state()
3156 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v8_0_set_pageflip_interrupt_state()
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H A Ddce_v6_0.c67 static const u32 crtc_offsets[6] = variable
229 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v6_0_crtc_get_scanoutpos()
397 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v6_0_is_display_hung()
443 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce()
446 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v6_0_disable_dce()
447 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce()
449 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
450 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v6_0_disable_dce()
3138 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v6_0_set_pageflip_interrupt_state()
3141 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v6_0_set_pageflip_interrupt_state()
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