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Searched refs:crg (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi161 resets = <&crg 0xbc 4>;
182 resets = <&crg 0xbc 6>;
269 clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
335 clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
349 resets = <&crg 0x9c 4>;
363 resets = <&crg 0xa0 4>;
569 <&crg 0xcc 10>,
584 <&crg 0xcc 11>,
621 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
652 <&crg 0xb8 16>,
[all …]
H A Dhi3670.dtsi186 compatible = "hisilicon,hi3670-media1-crg", "syscon";
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
/linux-6.15/drivers/clk/hisilicon/
H A Dclk-hi3519.c134 crg->clk_data); in hi3519_clk_unregister()
137 crg->clk_data); in hi3519_clk_unregister()
140 crg->clk_data); in hi3519_clk_unregister()
145 struct hi3519_crg_data *crg; in hi3519_clk_probe() local
147 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); in hi3519_clk_probe()
148 if (!crg) in hi3519_clk_probe()
152 if (!crg->rstc) in hi3519_clk_probe()
156 if (IS_ERR(crg->clk_data)) { in hi3519_clk_probe()
157 hisi_reset_exit(crg->rstc); in hi3519_clk_probe()
158 return PTR_ERR(crg->clk_data); in hi3519_clk_probe()
[all …]
H A Dcrg-hi3516cv300.c240 crg->clk_data); in hi3516cv300_sysctrl_clk_unregister()
263 struct hisi_crg_dev *crg; in hi3516cv300_crg_probe() local
265 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); in hi3516cv300_crg_probe()
266 if (!crg) in hi3516cv300_crg_probe()
270 if (!crg->funcs) in hi3516cv300_crg_probe()
274 if (!crg->rstc) in hi3516cv300_crg_probe()
277 crg->clk_data = crg->funcs->register_clks(pdev); in hi3516cv300_crg_probe()
278 if (IS_ERR(crg->clk_data)) { in hi3516cv300_crg_probe()
279 hisi_reset_exit(crg->rstc); in hi3516cv300_crg_probe()
280 return PTR_ERR(crg->clk_data); in hi3516cv300_crg_probe()
[all …]
H A Dcrg-hi3798cv200.c262 crg->clk_data); in hi3798cv200_clk_unregister()
265 crg->clk_data); in hi3798cv200_clk_unregister()
268 crg->clk_data); in hi3798cv200_clk_unregister()
327 crg->clk_data); in hi3798cv200_sysctrl_clk_unregister()
346 struct hisi_crg_dev *crg; in hi3798cv200_crg_probe() local
348 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); in hi3798cv200_crg_probe()
349 if (!crg) in hi3798cv200_crg_probe()
353 if (!crg->funcs) in hi3798cv200_crg_probe()
357 if (!crg->rstc) in hi3798cv200_crg_probe()
360 crg->clk_data = crg->funcs->register_clks(pdev); in hi3798cv200_crg_probe()
[all …]
H A Dclk-hi3559a.c786 struct hisi_crg_dev *crg; in hi3559av100_crg_probe() local
788 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); in hi3559av100_crg_probe()
789 if (!crg) in hi3559av100_crg_probe()
793 if (!crg->funcs) in hi3559av100_crg_probe()
797 if (!crg->rstc) in hi3559av100_crg_probe()
800 crg->clk_data = crg->funcs->register_clks(pdev); in hi3559av100_crg_probe()
801 if (IS_ERR(crg->clk_data)) { in hi3559av100_crg_probe()
802 hisi_reset_exit(crg->rstc); in hi3559av100_crg_probe()
803 return PTR_ERR(crg->clk_data); in hi3559av100_crg_probe()
806 platform_set_drvdata(pdev, crg); in hi3559av100_crg_probe()
[all …]
H A DMakefile11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
16 obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
/linux-6.15/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi37 crg: clock-reset-controller@12010000 { label
38 compatible = "hisilicon,hi3519-crg";
55 clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
64 clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
73 clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
82 clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
91 clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
130 clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
142 clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
154 clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dphy-hisi-inno-usb2.txt39 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
40 resets = <&crg 0xbc 4>;
47 resets = <&crg 0xbc 8>;
53 resets = <&crg 0xbc 9>;
60 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
61 resets = <&crg 0xbc 6>;
68 resets = <&crg 0xbc 10>;
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dhisilicon-histb-pcie.txt60 clocks = <&crg PCIE_AUX_CLK>,
61 <&crg PCIE_PIPE_CLK>,
62 <&crg PCIE_SYS_CLK>,
63 <&crg PCIE_BUS_CLK>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
/linux-6.15/Documentation/devicetree/bindings/usb/
H A Dhisilicon,histb-xhci.txt36 clocks = <&crg HISTB_USB3_BUS_CLK>,
37 <&crg HISTB_USB3_UTMI_CLK>,
38 <&crg HISTB_USB3_PIPE_CLK>,
39 <&crg HISTB_USB3_SUSPEND_CLK>;
41 resets = <&crg 0xb0 12>;
H A Dhisilicon,hi3798mv200-dwc3.yaml83 resets = <&crg 0xb0 12>;
/linux-6.15/Documentation/devicetree/bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml80 clocks = <&crg HISTB_MMC_CIU_CLK>,
81 <&crg HISTB_MMC_BIU_CLK>,
82 <&crg HISTB_MMC_SAMPLE_CLK>,
83 <&crg HISTB_MMC_DRV_CLK>;
85 resets = <&crg 0xa0 4>;
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dhisilicon-hix5hd2-gmac.txt51 clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
53 resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
H A Dhisilicon-femac.txt34 clocks = <&crg HI3518EV200_ETH_CLK>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
H A Dhisilicon-femac-mdio.txt15 clocks = <&crg HI3516CV300_MDIO_CLK>;
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dhisi-crg.txt13 - "hisilicon,hi3516cv300-crg"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
38 compatible = "hisilicon,hi3519-crg";
H A Dstarfive,jh7110-ispcrg.yaml42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-voutcrg.yaml44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
70 #include <dt-bindings/clock/starfive,jh7110-crg.h>
72 #include <dt-bindings/reset/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-stgcrg.yaml44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Dstarfive,jh7110-aoncrg.yaml71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
H A Dhi3670-clock.txt16 - "hisilicon,hi3670-media1-crg"
17 - "hisilicon,hi3670-media2-crg"
H A Dstarfive,jh7110-syscrg.yaml82 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
87 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
H A Dstarfive,jh7110-pll.yaml31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
/linux-6.15/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml57 clocks = <&crg 42>;
58 resets = <&crg 0x188 4>;
59 assigned-clocks = <&crg 42>;

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