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Searched refs:cpuc (Results 1 – 25 of 27) sorted by relevance

12

/linux-6.15/arch/alpha/kernel/
H A Dperf_event.c422 cpuc->idx_mask |= (1<<cpuc->current_idx[j]); in maybe_change_configuration()
424 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
462 if (!alpha_check_constraints(cpuc->event, cpuc->evtype, n0+1)) { in alpha_pmu_add()
464 cpuc->n_added++; in alpha_pmu_add()
503 cpuc->event[j - 1] = cpuc->event[j]; in alpha_pmu_del()
504 cpuc->evtype[j - 1] = cpuc->evtype[j]; in alpha_pmu_del()
547 if (cpuc->enabled) in alpha_pmu_stop()
568 if (cpuc->enabled) in alpha_pmu_start()
720 if (cpuc->enabled) in alpha_pmu_enable()
723 cpuc->enabled = 1; in alpha_pmu_enable()
[all …]
/linux-6.15/arch/x86/events/amd/
H A Dlbr.c144 cpuc->lbr_entries[j - 1] = cpuc->lbr_entries[j]; in amd_pmu_lbr_filter()
145 cpuc->lbr_stack.nr--; in amd_pmu_lbr_filter()
167 if (!cpuc->lbr_users) in amd_pmu_lbr_read()
211 cpuc->lbr_stack.nr = out; in amd_pmu_lbr_read()
217 cpuc->lbr_stack.hw_idx = 0; in amd_pmu_lbr_read()
335 cpuc->last_log_id = 0; in amd_pmu_lbr_reset()
348 cpuc->lbr_select = 1; in amd_pmu_lbr_add()
350 cpuc->br_sel = reg->reg; in amd_pmu_lbr_add()
367 cpuc->lbr_select = 0; in amd_pmu_lbr_del()
369 cpuc->lbr_users--; in amd_pmu_lbr_del()
[all …]
H A Dcore.c491 if (cpuc->is_fake) in __amd_get_nb_event_constraints()
582 if (!cpuc->lbr_sel) in amd_pmu_cpu_prepare()
591 if (cpuc->amd_nb) in amd_pmu_cpu_prepare()
594 kfree(cpuc->lbr_sel); in amd_pmu_cpu_prepare()
595 cpuc->lbr_sel = NULL; in amd_pmu_cpu_prepare()
622 *onln = cpuc->amd_nb; in amd_pmu_cpu_starting()
623 cpuc->amd_nb = nb; in amd_pmu_cpu_starting()
894 cpuc->enabled = 0; in amd_pmu_handle_irq()
899 if (cpuc->lbr_users) in amd_pmu_handle_irq()
959 cpuc->enabled = 0; in amd_pmu_v2_handle_irq()
[all …]
H A Dbrs.c205 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in amd_brs_enable() local
209 if (++cpuc->brs_active > 1) in amd_brs_enable()
222 if (cpuc->lbr_users) in amd_brs_enable_all()
232 if (!cpuc->brs_active) in amd_brs_disable()
236 if (--cpuc->brs_active) in amd_brs_disable()
258 if (cpuc->lbr_users) in amd_brs_disable_all()
284 struct perf_event *event = cpuc->events[0]; in amd_brs_drain()
285 struct perf_branch_entry *br = cpuc->lbr_entries; in amd_brs_drain()
355 cpuc->lbr_stack.nr = nr; in amd_brs_drain()
390 if (!cpuc->lbr_users) in amd_pmu_brs_sched_task()
[all …]
/linux-6.15/arch/x86/events/intel/
H A Dlbr.c137 if (cpuc->lbr_sel) in __intel_pmu_lbr_enable()
200 cpuc->last_log_id = 0; in intel_pmu_lbr_reset()
385 if (cpuc->lbr_select) in intel_pmu_lbr_restore()
477 if (cpuc->lbr_select) in intel_pmu_lbr_save()
532 if (!cpuc->lbr_users) in intel_pmu_lbr_sched_task()
685 cpuc->lbr_users--; in intel_pmu_lbr_del()
782 if (cpuc->lbr_sel) { in intel_pmu_lbr_read_64()
1022 cpuc->lbr_users == cpuc->lbr_pebs_users) in intel_pmu_lbr_read()
1264 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; in intel_pmu_lbr_filter()
1265 cpuc->lbr_counters[j-1] = cpuc->lbr_counters[j]; in intel_pmu_lbr_filter()
[all …]
H A Dds.c853 if (!cpuc->ds) in intel_pmu_disable_bts()
1258 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) in pebs_needs_sched_cb()
1261 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); in pebs_needs_sched_cb()
1287 if (cpuc->n_pebs == cpuc->n_large_pebs) { in pebs_update_threshold()
1475 cpuc->n_pebs++; in intel_pmu_pebs_add()
1477 cpuc->n_large_pebs++; in intel_pmu_pebs_add()
1525 if (cpuc->n_pebs == cpuc->n_large_pebs && in intel_pmu_drain_large_pebs()
1526 cpuc->n_pebs != cpuc->n_pebs_via_pt) in intel_pmu_drain_large_pebs()
1593 cpuc->n_pebs--; in intel_pmu_pebs_del()
1619 if (cpuc->enabled) in intel_pmu_pebs_disable()
[all …]
H A Dcore.c2308 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { in __intel_pmu_enable_all()
2310 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; in __intel_pmu_enable_all()
2805 cpuc->enabled = 0; in intel_pmu_read_event()
3021 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; in x86_pmu_handle_guest_pebs()
3216 cpuc->enabled = 0; in intel_pmu_handle_irq()
3763 if (cpuc->is_fake) in intel_put_excl_constraints()
4397 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, in intel_guest_get_msrs()
5144 cpuc->pmu = NULL; in init_hybrid_pmu()
5230 cpuc->kfree_on_online[0] = cpuc->shared_regs; in intel_pmu_cpu_starting()
5240 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; in intel_pmu_cpu_starting()
[all …]
H A Dbts.c262 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in bts_event_start() local
273 bts->ds_back.bts_buffer_base = cpuc->ds->bts_buffer_base; in bts_event_start()
274 bts->ds_back.bts_absolute_maximum = cpuc->ds->bts_absolute_maximum; in bts_event_start()
275 bts->ds_back.bts_interrupt_threshold = cpuc->ds->bts_interrupt_threshold; in bts_event_start()
307 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in bts_event_stop() local
332 cpuc->ds->bts_index = bts->ds_back.bts_buffer_base; in bts_event_stop()
333 cpuc->ds->bts_buffer_base = bts->ds_back.bts_buffer_base; in bts_event_stop()
334 cpuc->ds->bts_absolute_maximum = bts->ds_back.bts_absolute_maximum; in bts_event_stop()
335 cpuc->ds->bts_interrupt_threshold = bts->ds_back.bts_interrupt_threshold; in bts_event_stop()
537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in bts_event_add() local
[all …]
H A Dknc.c216 struct cpu_hw_events *cpuc; in knc_pmu_handle_irq() local
221 cpuc = this_cpu_ptr(&cpu_hw_events); in knc_pmu_handle_irq()
243 struct perf_event *event = cpuc->events[bit]; in knc_pmu_handle_irq()
247 if (!test_bit(bit, cpuc->active_mask)) in knc_pmu_handle_irq()
268 if (cpuc->enabled) in knc_pmu_handle_irq()
H A Dp4.c920 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in p4_pmu_disable_all() local
924 struct perf_event *event = cpuc->events[idx]; in p4_pmu_disable_all()
925 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_disable_all()
999 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in p4_pmu_enable_all() local
1003 struct perf_event *event = cpuc->events[idx]; in p4_pmu_enable_all()
1004 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_enable_all()
1036 struct cpu_hw_events *cpuc; in p4_pmu_handle_irq() local
1042 cpuc = this_cpu_ptr(&cpu_hw_events); in p4_pmu_handle_irq()
1047 if (!test_bit(idx, cpuc->active_mask)) { in p4_pmu_handle_irq()
1054 event = cpuc->events[idx]; in p4_pmu_handle_irq()
[all …]
/linux-6.15/arch/x86/events/
H A Dcore.c1154 cpuc->n_pair++; in collect_event()
1301 int n_running = cpuc->n_events - cpuc->n_added; in x86_pmu_enable()
1653 if (i >= cpuc->n_events - cpuc->n_added) in x86_pmu_del()
1660 cpuc->event_list[i-1] = cpuc->event_list[i]; in x86_pmu_del()
1661 cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; in x86_pmu_del()
1662 cpuc->assign[i-1] = cpuc->assign[i]; in x86_pmu_del()
2323 kfree(cpuc); in free_fake_cpuc()
2331 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); in allocate_fake_cpuc()
2332 if (!cpuc) in allocate_fake_cpuc()
2350 return cpuc; in allocate_fake_cpuc()
[all …]
H A Dperf_event.h825 (*get_event_constraints)(struct cpu_hw_events *cpuc,
832 void (*start_scheduling)(struct cpu_hw_events *cpuc);
836 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
937 void (*lbr_read)(struct cpu_hw_events *cpuc);
1432 cpuc->lbr_users++; in amd_pmu_brs_add()
1443 cpuc->lbr_users--; in amd_pmu_brs_del()
1444 WARN_ON_ONCE(cpuc->lbr_users < 0); in amd_pmu_brs_del()
1565 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1653 struct cpu_hw_events *cpuc,
1677 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
[all …]
/linux-6.15/arch/sparc/kernel/
H A Dperf_event.c977 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; in calculate_single_pcr()
1019 if (cpuc->n_added) in update_pcrs_for_enable()
1034 if (cpuc->enabled) in sparc_pmu_enable()
1037 cpuc->enabled = 1; in sparc_pmu_enable()
1055 cpuc->enabled = 0; in sparc_pmu_disable()
1133 cpuc->event[i - 1] = cpuc->event[i]; in sparc_pmu_del()
1134 cpuc->events[i - 1] = cpuc->events[i]; in sparc_pmu_del()
1402 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) in sparc_pmu_add()
1406 cpuc->n_events++; in sparc_pmu_add()
1407 cpuc->n_added++; in sparc_pmu_add()
[all …]
/linux-6.15/tools/sched_ext/
H A Dscx_qmap.bpf.c368 struct cpu_ctx *cpuc; in BPF_STRUCT_OPS() local
401 if (!cpuc->dsp_cnt) { in BPF_STRUCT_OPS()
402 cpuc->dsp_idx = (cpuc->dsp_idx + 1) % 5; in BPF_STRUCT_OPS()
403 cpuc->dsp_cnt = 1 << cpuc->dsp_idx; in BPF_STRUCT_OPS()
438 cpuc->dsp_cnt--; in BPF_STRUCT_OPS()
445 if (!cpuc->dsp_cnt) in BPF_STRUCT_OPS()
449 cpuc->dsp_cnt = 0; in BPF_STRUCT_OPS()
470 struct cpu_ctx *cpuc; in BPF_STRUCT_OPS() local
484 cpuc->avg_weight = cpuc->avg_weight * 3 / 4 + p->scx.weight / 4; in BPF_STRUCT_OPS()
593 struct cpu_ctx *cpuc; in BPF_STRUCT_OPS() local
[all …]
H A Dscx_flatcg.bpf.c152 struct fcg_cpu_ctx *cpuc; in find_cpu_ctx() local
155 cpuc = bpf_map_lookup_elem(&cpu_ctx, &idx); in find_cpu_ctx()
156 if (!cpuc) { in find_cpu_ctx()
160 return cpuc; in find_cpu_ctx()
729 struct fcg_cpu_ctx *cpuc; in BPF_STRUCT_OPS() local
735 cpuc = find_cpu_ctx(); in BPF_STRUCT_OPS()
736 if (!cpuc) in BPF_STRUCT_OPS()
739 if (!cpuc->cur_cgid) in BPF_STRUCT_OPS()
756 cgrp = bpf_cgroup_from_id(cpuc->cur_cgid); in BPF_STRUCT_OPS()
781 cpuc->cur_at = now; in BPF_STRUCT_OPS()
[all …]
/linux-6.15/arch/loongarch/kernel/
H A Dperf_event.c258 if (!test_and_set_bit(i, cpuc->used_mask)) in loongarch_pmu_alloc_counter()
269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in loongarch_pmu_enable_event() local
293 cpuc->saved_ctrl[idx] = loongarch_pmu_read_control(idx) & in loongarch_pmu_disable_event()
295 loongarch_pmu_write_control(idx, cpuc->saved_ctrl[idx]); in loongarch_pmu_disable_event()
394 idx = loongarch_pmu_alloc_counter(cpuc, hwc); in loongarch_pmu_add()
406 cpuc->events[idx] = event; in loongarch_pmu_add()
429 cpuc->events[idx] = NULL; in loongarch_pmu_del()
430 clear_bit(idx, cpuc->used_mask); in loongarch_pmu_del()
474 struct perf_event *event = cpuc->events[idx]; in handle_associated_event()
509 if (test_bit(n, cpuc->used_mask)) { in pmu_handle_irq()
[all …]
/linux-6.15/arch/sh/kernel/
H A Dperf_event.c201 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in sh_pmu_stop() local
207 cpuc->events[idx] = NULL; in sh_pmu_stop()
219 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in sh_pmu_start() local
229 cpuc->events[idx] = event; in sh_pmu_start()
236 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in sh_pmu_del() local
239 __clear_bit(event->hw.idx, cpuc->used_mask); in sh_pmu_del()
246 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); in sh_pmu_add() local
253 if (__test_and_set_bit(idx, cpuc->used_mask)) { in sh_pmu_add()
254 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); in sh_pmu_add()
258 __set_bit(idx, cpuc->used_mask); in sh_pmu_add()
/linux-6.15/drivers/perf/
H A Darm_xscale_pmu.c149 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); in xscale1pmu_handle_irq() local
174 struct perf_event *event = cpuc->events[idx]; in xscale1pmu_handle_irq()
267 xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc, in xscale1pmu_get_event_idx() argument
272 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) in xscale1pmu_get_event_idx()
277 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) in xscale1pmu_get_event_idx()
280 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) in xscale1pmu_get_event_idx()
290 clear_bit(event->hw.idx, cpuc->used_mask); in xscalepmu_clear_event_idx()
507 struct perf_event *event = cpuc->events[idx]; in xscale2pmu_handle_irq()
628 xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc, in xscale2pmu_get_event_idx() argument
631 int idx = xscale1pmu_get_event_idx(cpuc, event); in xscale2pmu_get_event_idx()
[all …]
H A Driscv_pmu.c260 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); in riscv_pmu_add() local
269 cpuc->events[idx] = event; in riscv_pmu_add()
270 cpuc->n_events++; in riscv_pmu_add()
284 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); in riscv_pmu_del() local
288 cpuc->events[hwc->idx] = NULL; in riscv_pmu_del()
292 cpuc->n_events--; in riscv_pmu_del()
390 struct cpu_hw_events *cpuc; in riscv_pmu_alloc() local
403 cpuc = per_cpu_ptr(pmu->hw_events, cpuid); in riscv_pmu_alloc()
404 cpuc->n_events = 0; in riscv_pmu_alloc()
406 cpuc->events[i] = NULL; in riscv_pmu_alloc()
[all …]
H A Darm_v6_pmu.c242 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); in armv6pmu_handle_irq() local
259 struct perf_event *event = cpuc->events[idx]; in armv6pmu_handle_irq()
314 armv6pmu_get_event_idx(struct pmu_hw_events *cpuc, in armv6pmu_get_event_idx() argument
320 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) in armv6pmu_get_event_idx()
329 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) in armv6pmu_get_event_idx()
332 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) in armv6pmu_get_event_idx()
340 static void armv6pmu_clear_event_idx(struct pmu_hw_events *cpuc, in armv6pmu_clear_event_idx() argument
343 clear_bit(event->hw.idx, cpuc->used_mask); in armv6pmu_clear_event_idx()
H A Darm_pmuv3.c775 for_each_set_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { in armv8pmu_enable_user_access()
776 if (armv8pmu_event_has_user_read(cpuc->events[i])) in armv8pmu_enable_user_access()
865 struct perf_event *event = cpuc->events[idx]; in armv8pmu_handle_irq()
904 if (!test_and_set_bit(idx, cpuc->used_mask)) in armv8pmu_get_single_idx()
922 if (!test_and_set_bit(idx, cpuc->used_mask)) { in armv8pmu_get_chain_idx()
924 if (!test_and_set_bit(idx - 1, cpuc->used_mask)) in armv8pmu_get_chain_idx()
927 clear_bit(idx, cpuc->used_mask); in armv8pmu_get_chain_idx()
968 return armv8pmu_get_chain_idx(cpuc, cpu_pmu); in armv8pmu_get_event_idx()
970 return armv8pmu_get_single_idx(cpuc, cpu_pmu); in armv8pmu_get_event_idx()
978 clear_bit(idx, cpuc->used_mask); in armv8pmu_clear_event_idx()
[all …]
H A Darm_v7_pmu.c993 clear_bit(event->hw.idx, cpuc->used_mask); in armv7pmu_clear_event_idx()
1536 if (test_and_set_bit(bit, cpuc->used_mask)) in krait_pmu_get_event_idx()
1540 idx = armv7pmu_get_event_idx(cpuc, event); in krait_pmu_get_event_idx()
1542 clear_bit(bit, cpuc->used_mask); in krait_pmu_get_event_idx()
1557 armv7pmu_clear_event_idx(cpuc, event); in krait_pmu_clear_event_idx()
1560 clear_bit(bit, cpuc->used_mask); in krait_pmu_clear_event_idx()
1843 if (test_and_set_bit(bit, cpuc->used_mask)) in scorpion_pmu_get_event_idx()
1847 idx = armv7pmu_get_event_idx(cpuc, event); in scorpion_pmu_get_event_idx()
1849 clear_bit(bit, cpuc->used_mask); in scorpion_pmu_get_event_idx()
1864 armv7pmu_clear_event_idx(cpuc, event); in scorpion_pmu_clear_event_idx()
[all …]
H A Dapple_m1_cpu_pmu.c446 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); in m1_pmu_handle_irq() local
466 struct perf_event *event = cpuc->events[idx]; in m1_pmu_handle_irq()
497 static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, in m1_pmu_get_event_idx() argument
513 if (!test_and_set_bit(idx, cpuc->used_mask)) in m1_pmu_get_event_idx()
520 static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, in m1_pmu_clear_event_idx() argument
523 clear_bit(event->hw.idx, cpuc->used_mask); in m1_pmu_clear_event_idx()
/linux-6.15/arch/mips/kernel/
H A Dperf_event_mipsxx.c341 !test_and_set_bit(i, cpuc->used_mask)) in mipsxx_pmu_alloc_counter()
369 cpuc->saved_ctrl[idx] |= in mipsxx_pmu_enable_event()
374 cpuc->saved_ctrl[idx] |= M_TC_EN_ALL; in mipsxx_pmu_enable_event()
387 cpuc->saved_ctrl[idx] |= ctrl; in mipsxx_pmu_enable_event()
509 idx = mipsxx_pmu_alloc_counter(cpuc, hwc); in mipspmu_add()
521 cpuc->events[idx] = event; in mipspmu_add()
544 cpuc->events[idx] = NULL; in mipspmu_del()
545 clear_bit(idx, cpuc->used_mask); in mipspmu_del()
786 struct perf_event *event = cpuc->events[idx]; in handle_associated_event()
1601 if (!test_bit(n, cpuc->used_mask)) in mipsxx_pmu_handle_shared_irq()
[all …]
/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c357 struct cpu_hw_events *cpuc; in zhaoxin_pmu_handle_irq() local
362 cpuc = this_cpu_ptr(&cpu_hw_events); in zhaoxin_pmu_handle_irq()
387 struct perf_event *event = cpuc->events[bit]; in zhaoxin_pmu_handle_irq()
391 if (!test_bit(bit, cpuc->active_mask)) in zhaoxin_pmu_handle_irq()
422 zhaoxin_get_event_constraints(struct cpu_hw_events *cpuc, int idx, in zhaoxin_get_event_constraints() argument

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