Home
last modified time | relevance | path

Searched refs:cp_mqd_base_addr_hi (Results 1 – 25 of 26) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/amd/include/
H A Dcik_structs.h80 uint32_t cp_mqd_base_addr_hi; member
H A Dvi_structs.h289 uint32_t cp_mqd_base_addr_hi; member
H A Dv12_structs.h157 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) member
804 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) member
H A Dv11_structs.h157 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) member
804 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) member
H A Dv10_structs.h157 uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) member
805 uint32_t cp_mqd_base_addr_hi; member
H A Dv9_structs.h299 uint32_t cp_mqd_base_addr_hi; member
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c129 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
H A Dkfd_mqd_manager_cik.c117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
H A Dkfd_mqd_manager_v10.c115 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
H A Dkfd_mqd_manager_vi.c117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
H A Dkfd_mqd_manager_v11.c162 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
H A Dkfd_mqd_manager_v9.c192 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v10_3.c316 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c301 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v11()
H A Dmes_v11_0.c1115 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v11_0_mqd_init()
1206 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1199 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v12_0_mqd_init()
1297 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in mes_v12_0_queue_init_register()
H A Damdgpu_amdkfd_gfx_v10.c330 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
H A Damdgpu_amdkfd_gfx_v9.c341 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
H A Dgfx_v12_0.c2902 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v12_0_gfx_mqd_init()
3072 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v12_0_compute_mqd_init()
3197 mqd->cp_mqd_base_addr_hi); in gfx_v12_0_kiq_init_register()
H A Dgfx_v9_4_3.c1841 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in gfx_v9_4_3_xcc_mqd_init()
1953 mqd->cp_mqd_base_addr_hi); in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v11_0.c4018 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
4185 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
4311 mqd->cp_mqd_base_addr_hi); in gfx_v11_0_kiq_init_register()
H A Dgfx_v9_0.c3586 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in gfx_v9_0_mqd_init()
3697 mqd->cp_mqd_base_addr_hi); in gfx_v9_0_kiq_init_register()
H A Dgfx_v10_0.c6738 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v10_0_gfx_mqd_init()
6921 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v10_0_compute_mqd_init()
7032 mqd->cp_mqd_base_addr_hi); in gfx_v10_0_kiq_init_register()
H A Dgfx_v7_0.c2847 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); in gfx_v7_0_mqd_init()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcik.c4435 u32 cp_mqd_base_addr_hi; member
4642 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); in cik_cp_compute_resume()
4644 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()

12