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Searched refs:cp_int_cntl_reg (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c1798 u32 tmp, cp_int_cntl_reg; in gfx_v12_0_enable_gui_idle_interrupt() local
1808 if (cp_int_cntl_reg) { in gfx_v12_0_enable_gui_idle_interrupt()
4629 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v12_0_set_gfx_eop_interrupt_state() local
4808 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_priv_reg_fault_state() local
4818 if (cp_int_cntl_reg) { in gfx_v12_0_set_priv_reg_fault_state()
4832 if (cp_int_cntl_reg) { in gfx_v12_0_set_priv_reg_fault_state()
4854 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_bad_op_fault_state() local
4864 if (cp_int_cntl_reg) { in gfx_v12_0_set_bad_op_fault_state()
4878 if (cp_int_cntl_reg) { in gfx_v12_0_set_bad_op_fault_state()
4899 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_priv_inst_fault_state() local
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H A Dgfx_v11_0.c2126 u32 tmp, cp_int_cntl_reg; in gfx_v11_0_enable_gui_idle_interrupt() local
2136 if (cp_int_cntl_reg) { in gfx_v11_0_enable_gui_idle_interrupt()
6167 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v11_0_set_gfx_eop_interrupt_state() local
6355 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_priv_reg_fault_state() local
6365 if (cp_int_cntl_reg) { in gfx_v11_0_set_priv_reg_fault_state()
6379 if (cp_int_cntl_reg) { in gfx_v11_0_set_priv_reg_fault_state()
6401 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_bad_op_fault_state() local
6411 if (cp_int_cntl_reg) { in gfx_v11_0_set_bad_op_fault_state()
6425 if (cp_int_cntl_reg) { in gfx_v11_0_set_bad_op_fault_state()
6446 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_priv_inst_fault_state() local
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H A Dgfx_v10_0.c5383 u32 tmp, cp_int_cntl_reg; in gfx_v10_0_enable_gui_idle_interrupt() local
5393 if (cp_int_cntl_reg) { in gfx_v10_0_enable_gui_idle_interrupt()
9035 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
9212 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_reg_fault_state() local
9222 if (cp_int_cntl_reg) { in gfx_v10_0_set_priv_reg_fault_state()
9236 if (cp_int_cntl_reg) { in gfx_v10_0_set_priv_reg_fault_state()
9258 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_bad_op_fault_state() local
9268 if (cp_int_cntl_reg) { in gfx_v10_0_set_bad_op_fault_state()
9282 if (cp_int_cntl_reg) { in gfx_v10_0_set_bad_op_fault_state()
9303 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_inst_fault_state() local
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H A Dgfx_v9_0.c6051 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_priv_reg_fault_state() local
6063 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); in gfx_v9_0_set_priv_reg_fault_state()
6065 if (cp_int_cntl_reg) { in gfx_v9_0_set_priv_reg_fault_state()
6066 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state()
6070 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6087 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_bad_op_fault_state() local
6099 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); in gfx_v9_0_set_bad_op_fault_state()
6101 if (cp_int_cntl_reg) { in gfx_v9_0_set_bad_op_fault_state()
6102 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state()
6106 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()