Home
last modified time | relevance | path

Searched refs:cp_int_cntl (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c3207 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3218 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3229 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3270 u32 cp_int_cntl; in gfx_v6_0_set_priv_reg_fault_state() local
3276 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3281 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3295 u32 cp_int_cntl; in gfx_v6_0_set_priv_inst_fault_state() local
3301 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_inst_fault_state()
[all …]
H A Dgfx_v12_0.c4648 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4650 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4656 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4658 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4808 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_priv_reg_fault_state() local
4820 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_priv_reg_fault_state()
4834 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_priv_reg_fault_state()
4854 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_bad_op_fault_state() local
4866 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_bad_op_fault_state()
4880 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v12_0_set_bad_op_fault_state()
[all …]
H A Dgfx_v11_0.c6189 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6191 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6197 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6199 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6355 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_priv_reg_fault_state() local
6367 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
6381 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_priv_reg_fault_state()
6401 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_bad_op_fault_state() local
6413 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_bad_op_fault_state()
6427 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v11_0_set_bad_op_fault_state()
[all …]
H A Dgfx_v7_0.c4627 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4631 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4633 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4636 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4638 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4701 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4707 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4712 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4726 u32 cp_int_cntl; in gfx_v7_0_set_priv_inst_fault_state() local
4732 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state()
[all …]
H A Dgfx_v10_0.c9035 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
9057 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9063 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9212 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_reg_fault_state() local
9224 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
9238 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_priv_reg_fault_state()
9258 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_bad_op_fault_state() local
9270 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_bad_op_fault_state()
9284 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v10_0_set_bad_op_fault_state()
9303 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_inst_fault_state() local
[all …]
H A Dgfx_v9_0.c6051 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_priv_reg_fault_state() local
6066 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state()
6067 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_priv_reg_fault_state()
6070 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6087 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_bad_op_fault_state() local
6102 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state()
6103 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_bad_op_fault_state()
6106 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dni.h32 int ring, u32 cp_int_cntl);
H A Devergreen.c4493 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4524 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4537 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4538 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4561 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4565 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
H A Dni.c1367 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1370 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
H A Dr600.c3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3821 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
H A Dsi.c6033 u32 cp_int_cntl; in si_irq_set() local
6051 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6083 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
H A Dcik.c7017 u32 cp_int_cntl; in cik_irq_set() local
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()