Home
last modified time | relevance | path

Searched refs:cntval_bits (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/arch/x86/events/intel/
H A Dp6.c227 .cntval_bits = 32,
H A Dknc.c307 .cntval_bits = 40,
H A Dp4.c1063 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) in p4_pmu_handle_irq()
1359 .cntval_bits = ARCH_P4_CNTRVAL_BITS,
H A Dds.c1982 int shift = 64 - x86_pmu.cntval_bits; in intel_perf_event_update_pmc()
2266 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
H A Dcore.c6630 x86_pmu.cntval_bits = eax.split.bit_width; in intel_pmu_init()
/linux-6.15/arch/x86/events/
H A Dcore.c121 int shift = 64 - x86_pmu.cntval_bits; in x86_perf_event_update()
1707 if (val & (1ULL << (x86_pmu.cntval_bits - 1))) in x86_pmu_handle_irq()
2059 pr_info("... bit width: %d\n", x86_pmu.cntval_bits); in x86_pmu_show_pmu_cap()
2726 userpg->pmc_width = x86_pmu.cntval_bits; in arch_perf_update_userpage()
3080 cap->bit_width_gp = x86_pmu.cntval_bits; in perf_get_x86_pmu_capability()
3081 cap->bit_width_fixed = x86_pmu.cntval_bits; in perf_get_x86_pmu_capability()
H A Dperf_event.h815 int cntval_bits; member
/linux-6.15/arch/x86/events/amd/
H A Dcore.c684 return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1)); in amd_pmu_test_overflow_topbit()
1326 .cntval_bits = 48,
/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c534 x86_pmu.cntval_bits = eax.split.bit_width; in zhaoxin_pmu_init()