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Searched refs:cmn_pll (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/clk/qcom/
H A Dipq-cmn-pll.c161 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_recalc_rate() local
168 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); in clk_cmn_pll_recalc_rate()
192 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_set_rate() local
229 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, in clk_cmn_pll_set_rate()
266 struct clk_cmn_pll *cmn_pll; in ipq_cmn_pll_clk_hw_register() local
279 cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); in ipq_cmn_pll_clk_hw_register()
280 if (!cmn_pll) in ipq_cmn_pll_clk_hw_register()
288 cmn_pll->hw.init = &init; in ipq_cmn_pll_clk_hw_register()
289 cmn_pll->regmap = regmap; in ipq_cmn_pll_clk_hw_register()
291 ret = devm_clk_hw_register(dev, &cmn_pll->hw); in ipq_cmn_pll_clk_hw_register()
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/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq9574-nsscc.yaml74 <&cmn_pll NSS_1200MHZ_CLK>,
75 <&cmn_pll PPE_353MHZ_CLK>,
H A Dqcom,ipq9574-cmn-pll.yaml66 cmn_pll: clock-controller@9b000 {
74 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dipq9574.dtsi351 cmn_pll: clock-controller@9b000 { label
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;