Searched refs:clock_state (Results 1 – 6 of 6) sorted by relevance
51 chip->clock_state = GD_CLOCK_UNDEF; in init_hw()92 u8 clock_state, spdif_status; in set_sample_rate() local99 clock_state = GD_CLOCK_44; in set_sample_rate()103 clock_state = GD_CLOCK_48; in set_sample_rate()107 clock_state = GD_CLOCK_NOCHANGE; in set_sample_rate()112 if (chip->clock_state == clock_state) in set_sample_rate()113 clock_state = GD_CLOCK_NOCHANGE; in set_sample_rate()118 chip->comm_page->gd_clock_state = clock_state; in set_sample_rate()123 if (clock_state != GD_CLOCK_NOCHANGE) in set_sample_rate()124 chip->clock_state = clock_state; in set_sample_rate()
55 chip->clock_state = GD_CLOCK_UNDEF; in init_hw()108 u8 clock_state, spdif_status; in set_sample_rate() local115 clock_state = GD_CLOCK_44; in set_sample_rate()119 clock_state = GD_CLOCK_48; in set_sample_rate()123 clock_state = GD_CLOCK_NOCHANGE; in set_sample_rate()128 if (chip->clock_state == clock_state) in set_sample_rate()129 clock_state = GD_CLOCK_NOCHANGE; in set_sample_rate()139 if (clock_state != GD_CLOCK_NOCHANGE) in set_sample_rate()140 chip->clock_state = clock_state; in set_sample_rate()157 chip->clock_state = GD_CLOCK_UNDEF; in set_input_clock()[all …]
376 u8 clock_state; /* Gina20, Darla20, Darla24 - only */ member
1137 schedule_work(&clock_state->out_work); in mlx5_pps_event()1368 if (IS_ERR(mdev->clock_state->compdev)) in mlx5_shared_clock_register()1390 mdev->clock_state->compdev = NULL; in mlx5_shared_clock_register()1525 clock_state = kzalloc(sizeof(*clock_state), GFP_KERNEL); in mlx5_init_clock()1526 if (!clock_state) in mlx5_init_clock()1528 clock_state->mdev = mdev; in mlx5_init_clock()1529 mdev->clock_state = clock_state; in mlx5_init_clock()1543 kfree(clock_state); in mlx5_init_clock()1544 mdev->clock_state = NULL; in mlx5_init_clock()1561 kfree(mdev->clock_state); in mlx5_cleanup_clock()[all …]
62 enum dm_pp_clocks_state clock_state; member
769 struct mlx5_clock_dev_state *clock_state; member