Searched refs:base_drexi0 (Results 1 – 1 of 1) sorted by relevance
157 void __iomem *base_drexi0; member389 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_set_bypass_dram_timings()392 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()396 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()429 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_dram_change_timings()432 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()850 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_perf_events_check()854 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_perf_events_check()907 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_disable_perf_events()1430 if (IS_ERR(dmc->base_drexi0)) in exynos5_dmc_probe()[all …]