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Searched refs:amdgpu_ip_version (Results 1 – 25 of 116) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c58 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) || in hdp_v4_0_invalidate_hdp()
59 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_invalidate_hdp()
60 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) in hdp_v4_0_invalidate_hdp()
92 if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
104 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
105 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
106 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
107 amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
141 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) || in hdp_v4_0_get_clockgating_state()
155 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { in hdp_v4_0_init_registers()
[all …]
H A Dpsp_v13_0.c96 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v13_0_init_microcode()
182 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader()
183 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || in psp_v13_0_wait_for_bootloader()
184 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? in psp_v13_0_wait_for_bootloader()
209 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader_steady_state()
210 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || in psp_v13_0_wait_for_bootloader_steady_state()
211 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { in psp_v13_0_wait_for_bootloader_steady_state()
780 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { in psp_v13_0_fatal_error_recovery_quirk()
810 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_get_ras_capability()
828 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) in psp_v13_0_is_aux_sos_load_required()
[all …]
H A Dgmc_v9_0.c702 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_process_interrupt()
1361 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { in gmc_v9_0_get_vbios_fb_size()
1464 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v9_0_set_umc_funcs()
1519 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_funcs()
1538 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_ras_funcs()
1576 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v9_0_set_mca_ras_funcs()
1619 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_init_nps_details()
1806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_mc_init()
2132 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_sw_init()
2225 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= in gmc_v9_0_sw_init()
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H A Dathub_v4_1_0.c34 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_get_cg_cntl()
47 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_cg_cntl()
96 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v4_1_0_set_clockgating()
H A Dvega20_ih.c322 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) && in vega20_ih_irq_init()
335 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) || in vega20_ih_irq_init()
336 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) || in vega20_ih_irq_init()
337 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) { in vega20_ih_irq_init()
367 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) || in vega20_ih_irq_init()
368 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) || in vega20_ih_irq_init()
369 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 4) || in vega20_ih_irq_init()
370 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5)) in vega20_ih_irq_init()
577 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) in vega20_ih_sw_init()
594 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) && in vega20_ih_sw_init()
[all …]
H A Dathub_v3_0.c41 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_get_cg_cntl()
57 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_set_cg_cntl()
110 switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) { in athub_v3_0_set_clockgating()
H A Dgmc_v10_0.c147 (amdgpu_ip_version(adev, GC_HWIP, 0) < in gmc_v10_0_process_interrupt()
315 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_gpu_tlb()
587 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v10_0_set_umc_funcs()
604 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v10_0_set_mmhub_funcs()
618 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_set_gfxhub_funcs()
734 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_mc_init()
801 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
819 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
1103 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { in gmc_v10_0_set_clockgating_state()
1112 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) in gmc_v10_0_set_clockgating_state()
[all …]
H A Dsoc15.c193 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
194 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
206 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc15_query_video_codecs()
349 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
350 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) in soc15_get_xclk()
356 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
550 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_asic_reset_method()
651 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_supports_baco()
989 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc15_common_early_init()
[all …]
H A Damdgpu_discovery.c1935 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
1990 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
2099 amdgpu_ip_version(adev, MP0_HWIP, 0)); in amdgpu_discovery_set_psp_ip_blocks()
2159 amdgpu_ip_version(adev, MP1_HWIP, 0)); in amdgpu_discovery_set_smu_ip_blocks()
2219 amdgpu_ip_version(adev, DCE_HWIP, 0)); in amdgpu_discovery_set_display_ip_blocks()
2235 amdgpu_ip_version(adev, DCI_HWIP, 0)); in amdgpu_discovery_set_display_ip_blocks()
2293 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gc_ip_blocks()
2350 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); in amdgpu_discovery_set_sdma_ip_blocks()
2369 amdgpu_ip_version(adev, UVD_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
2382 amdgpu_ip_version(adev, VCE_HWIP, 0)); in amdgpu_discovery_set_mm_ip_blocks()
[all …]
H A Dvpe_v6_1.c135 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
142 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_load_microcode()
283 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v_6_1_ring_stop()
290 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) { in vpe_v_6_1_ring_stop()
317 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
325 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_trap_irq_state()
361 if (amdgpu_ip_version(adev, VPE_HWIP, 0) == IP_VERSION(6, 1, 1)) in vpe_v6_1_set_regs()
H A Dhdp_v6_0.c60 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
70 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
135 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) in hdp_v6_0_update_clock_gating()
H A Dnbio_v7_2.c61 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_get_rev_id()
80 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_mc_access_enable()
264 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_update_medium_grain_light_sleep()
371 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
396 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_2_init_registers()
H A Dsoc24.c79 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc24_query_video_codecs()
204 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc24_asic_reset_method()
262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
388 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
544 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc24_common_set_clockgating_state()
564 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { in soc24_common_set_powergating_state()
H A Damdgpu_fw_attestation.c125 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 2) || in amdgpu_is_fw_attestation_supported()
126 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 3)) in amdgpu_is_fw_attestation_supported()
H A Dumsch_mm_v4_0.c64 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_load_microcode()
258 if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) { in umsch_mm_v4_0_ring_stop()
298 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
303 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
306 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
308 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
H A Damdgpu_sdma.c264 if ((amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in amdgpu_sdma_init_microcode()
266 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in amdgpu_sdma_init_microcode()
268 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in amdgpu_sdma_init_microcode()
532 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_sdma_is_shared_inv_eng()
533 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_sdma_is_shared_inv_eng()
534 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) in amdgpu_sdma_is_shared_inv_eng()
H A Dmmhub_v2_0.c154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_set_clockgating()
679 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_get_clockgating()
H A Dsdma_v4_0.c519 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { in sdma_v4_0_init_golden_registers()
589 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { in sdma_v4_0_setup_ulv()
628 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_init_microcode()
630 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_init_microcode()
1026 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_ctx_switch_enable()
1863 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_sw_init()
1885 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= in sdma_v4_0_sw_init()
1887 amdgpu_ip_version(adev, SDMA0_HWIP, 0) < in sdma_v4_0_sw_init()
1900 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_sw_init()
2090 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == in sdma_v4_0_process_trap_irq()
[all …]
H A Dgmc_v12_0.c535 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && in gmc_v12_0_get_dcc_alignment()
536 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) in gmc_v12_0_get_dcc_alignment()
567 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v12_0_set_umc_funcs()
584 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v12_0_set_mmhub_funcs()
595 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_set_gfxhub_funcs()
750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_sw_init()
H A Dgmc_v11_0.c550 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { in gmc_v11_0_set_umc_funcs()
573 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v11_0_set_mmhub_funcs()
593 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
657 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
759 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
767 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
H A Damdgpu_psp.c104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_check_pmfw_centralized_cstate_management()
132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_init_sriov_microcode()
173 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_early_init()
1402 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= in psp_xgmi_peer_link_info_supported()
1518 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
1520 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
2917 (amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
2919 amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
2921 amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
3629 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == in is_ta_fw_applicable()
[all …]
H A Daldebaran.c38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_is_mode2_default()
150 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_mode2_perform_reset()
325 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) == in aldebaran_mode2_restore_hwcontext()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_int_process_v9.c170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { in event_interrupt_poison_consumption_v9()
177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { in event_interrupt_poison_consumption_v9()
200 if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) { in event_interrupt_poison_consumption_v9()
207 } else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { in event_interrupt_poison_consumption_v9()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dyellow_carp_ppt.c1014 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1016 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1017 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1021 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1023 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1024 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1028 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1030 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1031 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
213 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_check_fw_version()
247 amdgpu_ip_version(adev, MP1_HWIP, 0)); in smu_v11_0_check_fw_version()
475 u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); in smu_v11_0_init_power()
735 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
736 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) || in smu_v11_0_init_display_count()
738 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1107 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_gfx_off_control()
1606 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_baco_set_state()
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