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Searched refs:amdgpu_ih_ring_init (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvega10_ih.c493 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true); in vega10_ih_sw_init()
501 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); in vega10_ih_sw_init()
508 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); in vega10_ih_sw_init()
518 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); in vega10_ih_sw_init()
H A Dvega20_ih.c580 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); in vega20_ih_sw_init()
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr); in vega20_ih_sw_init()
596 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); in vega20_ih_sw_init()
607 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr); in vega20_ih_sw_init()
H A Damdgpu_ih.h103 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
H A Dih_v6_0.c588 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); in ih_v6_0_sw_init()
596 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v6_0_sw_init()
608 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); in ih_v6_0_sw_init()
H A Dih_v6_1.c567 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); in ih_v6_1_sw_init()
575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v6_1_sw_init()
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); in ih_v6_1_sw_init()
H A Dih_v7_0.c557 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); in ih_v7_0_sw_init()
565 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, in ih_v7_0_sw_init()
577 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); in ih_v7_0_sw_init()
H A Dnavi10_ih.c573 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); in navi10_ih_sw_init()
586 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); in navi10_ih_sw_init()
H A Dsi_ih.c173 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in si_ih_sw_init()
H A Dcik_ih.c305 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in cik_ih_sw_init()
H A Damdgpu_ih.c41 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, in amdgpu_ih_ring_init() function
H A Diceland_ih.c295 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in iceland_ih_sw_init()
H A Dcz_ih.c296 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in cz_ih_sw_init()
H A Dtonga_ih.c305 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true); in tonga_ih_sw_init()