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Searched refs:__EVENT_CONSTRAINT (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/arch/x86/events/
H A Dperf_event.h374 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \ macro
378 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
413 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
512 __EVENT_CONSTRAINT(code, n, \
518 __EVENT_CONSTRAINT(code, n, \
528 __EVENT_CONSTRAINT(code, n, \
535 __EVENT_CONSTRAINT(code, n, \
540 __EVENT_CONSTRAINT(code, n, \
547 __EVENT_CONSTRAINT(code, n, \
552 __EVENT_CONSTRAINT(code, n, \
[all …]
H A Dcore.c2121 __EVENT_CONSTRAINT(0, x86_pmu.cntr_mask64, in init_hw_perf_events()
/linux-6.15/arch/x86/events/amd/
H A Dcore.c1264 __EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK, 1, 0, PERF_X86_EVENT_PAIR);
1466 __EVENT_CONSTRAINT(0, even_ctr_mask, 0, in amd_core_pmu_init()
/linux-6.15/arch/x86/events/intel/
H A Dlbr.c1711 __EVENT_CONSTRAINT(INTEL_FIXED_VLBR_EVENT, (1ULL << INTEL_PMC_IDX_FIXED_VLBR),
H A Duncore.c1016 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1, in uncore_type_init()
H A Dcore.c5076 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_check_hybrid_pmus()
6496 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_init_hybrid()
7272 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_init()