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Searched refs:_MMIO (Results 1 – 25 of 60) sorted by relevance

123

/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_gt_regs.h32 #define RPM_CONFIG0 _MMIO(0xd00)
43 #define RPM_CONFIG1 _MMIO(0xd04)
47 #define RCP_CONFIG _MMIO(0xd08)
94 #define HWS_PGA _MMIO(0x2080)
127 #define NOPID _MMIO(0x2094)
128 #define HWSTAM _MMIO(0x2098)
1398 #define ECR _MMIO(0x11600)
1404 #define EG0 _MMIO(0x11610)
1405 #define EG1 _MMIO(0x11614)
1406 #define EG2 _MMIO(0x11618)
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H A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
19 #define RING_START(base) _MMIO((base) + 0x38)
20 #define RING_CTL(base) _MMIO((base) + 0x3c)
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
68 #define IPEIR(base) _MMIO((base) + 0x88)
69 #define IPEHR(base) _MMIO((base) + 0x8c)
70 #define RING_ID(base) _MMIO((base) + 0x8c)
87 #define ACTHD(base) _MMIO((base) + 0xc8)
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/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
33 #define GUC_HEADER_INFO _MMIO(0xc014)
45 #define DMA_ADDR_0_LOW _MMIO(0xc300)
46 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
47 #define DMA_ADDR_1_LOW _MMIO(0xc308)
48 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
51 #define DMA_COPY_SIZE _MMIO(0xc310)
52 #define DMA_CTRL _MMIO(0xc314)
70 #define GUC_WOPCM_SIZE _MMIO(0xc050)
80 #define GEN8_GTCR _MMIO(0x4274)
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/linux-6.15/drivers/gpu/drm/i915/
H A Di915_perf_oa_regs.h11 #define GEN7_OACONTROL _MMIO(0x2360)
28 #define GEN8_OACTXID _MMIO(0x2364)
30 #define GEN8_OA_DEBUG _MMIO(0x2B04)
36 #define GEN8_OACONTROL _MMIO(0x2B00)
45 #define GEN8_OACTXCONTROL _MMIO(0x2360)
58 #define GEN8_OABUFFER _MMIO(0x2b14)
61 #define GEN7_OASTATUS1 _MMIO(0x2364)
67 #define GEN7_OASTATUS2 _MMIO(0x2368)
71 #define GEN8_OASTATUS _MMIO(0x2b08)
79 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
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H A Dintel_gvt_mmio_table.c83 MMIO_D(_MMIO(0x2148)); in iterate_generic_mmio()
106 MMIO_D(_MMIO(0x2124)); in iterate_generic_mmio()
107 MMIO_D(_MMIO(0x20dc)); in iterate_generic_mmio()
109 MMIO_D(_MMIO(0x2088)); in iterate_generic_mmio()
111 MMIO_D(_MMIO(0x2470)); in iterate_generic_mmio()
115 MMIO_D(_MMIO(0x9030)); in iterate_generic_mmio()
116 MMIO_D(_MMIO(0x20a0)); in iterate_generic_mmio()
117 MMIO_D(_MMIO(0x2420)); in iterate_generic_mmio()
118 MMIO_D(_MMIO(0x2430)); in iterate_generic_mmio()
119 MMIO_D(_MMIO(0x2434)); in iterate_generic_mmio()
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H A Dintel_mchbar_regs.h32 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
43 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
47 #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
48 #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
51 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
69 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
71 #define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)
73 #define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)
74 #define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)
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H A Di915_reg.h416 #define DERRMR _MMIO(0x44050)
440 #define GEN2_IER _MMIO(0x20a0)
441 #define GEN2_IIR _MMIO(0x20a4)
442 #define GEN2_IMR _MMIO(0x20a8)
466 #define EIR _MMIO(0x20b0)
467 #define EMR _MMIO(0x20b4)
468 #define ESR _MMIO(0x20b8)
500 #define FW_BLC _MMIO(0x20d8)
716 #define VGA0 _MMIO(0x6000)
717 #define VGA1 _MMIO(0x6004)
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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
82 #define TV_DAC _MMIO(0x68004)
133 #define TV_CSC_Y _MMIO(0x68010)
139 #define TV_CSC_Y2 _MMIO(0x68014)
150 #define TV_CSC_U _MMIO(0x68018)
156 #define TV_CSC_U2 _MMIO(0x6801c)
167 #define TV_CSC_V _MMIO(0x68020)
173 #define TV_CSC_V2 _MMIO(0x68024)
206 #define TV_H_CTL_1 _MMIO(0x68030)
214 #define TV_H_CTL_2 _MMIO(0x68034)
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H A Dintel_combo_phy_regs.h27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
46 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
54 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
57 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
59 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
69 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
72 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
74 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
107 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
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H A Dintel_dmc_regs.h11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
68 #define DMC_SSP_BASE _MMIO(0x8F074)
69 #define DMC_HTP_SKL _MMIO(0x8F004)
70 #define DMC_LAST_WRITE _MMIO(0x8F034)
90 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
91 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
97 #define TGL_DMC_DEBUG3 _MMIO(0x101090)
98 #define DG1_DMC_DEBUG3 _MMIO(0x13415c)
100 #define DMC_WAKELOCK_CFG _MMIO(0x8F1B0)
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H A Di9xx_wm_regs.h82 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
89 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
98 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
228 #define WM1_LP_ILK _MMIO(0x45108)
229 #define WM2_LP_ILK _MMIO(0x4510c)
230 #define WM3_LP_ILK _MMIO(0x45110)
242 #define WM1S_LP_ILK _MMIO(0x45120)
243 #define WM2S_LP_IVB _MMIO(0x45124)
244 #define WM3S_LP_IVB _MMIO(0x45128)
249 #define WM_MISC _MMIO(0x45260)
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H A Dintel_fbc_regs.h11 #define FBC_CONTROL _MMIO(0x3208)
23 #define FBC_COMMAND _MMIO(0x320c)
25 #define FBC_STATUS _MMIO(0x3210)
53 #define DPFC_CB_BASE _MMIO(0x3200)
55 #define DPFC_CONTROL _MMIO(0x3208)
76 #define DPFC_RECOMP_CTL _MMIO(0x320c)
81 #define DPFC_STATUS _MMIO(0x3210)
85 #define DPFC_STATUS2 _MMIO(0x3214)
88 #define DPFC_FENCE_YOFF _MMIO(0x3218)
90 #define DPFC_CHICKEN _MMIO(0x3224)
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H A Dintel_vdsc_regs.h12 #define DSS_CTL1 _MMIO(0x67400)
23 #define DSS_CTL2 _MMIO(0x67404)
54 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
55 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
200 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
202 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
225 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
227 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
251 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
253 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
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H A Dintel_dsb_regs.h15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
53 #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
73 #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
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H A Dintel_audio_regs.h11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
39 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
124 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
127 #define AUD_FREQ_CNTRL _MMIO(0x65900)
128 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
131 #define AUD_TS_CDCLK_M _MMIO(0x65ea0)
133 #define AUD_TS_CDCLK_N _MMIO(0x65ea4)
136 #define AUD_CONFIG_BE _MMIO(0x65ef0)
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H A Dskl_watermark_regs.h31 #define MBUS_UBOX_CTL _MMIO(0x4503C)
32 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
33 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
35 #define MBUS_CTL _MMIO(0x4438C)
58 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \
70 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780)
71 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784)
72 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788)
76 #define MTL_LATENCY_SAGV _MMIO(0x4578c)
79 #define LNL_PKG_C_LATENCY _MMIO(0x46460)
H A Dintel_display_reg_defs.h25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
27 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
28 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
30 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
32 #define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c…
33 #define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c…
39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \
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H A Dintel_backlight_regs.h24 #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */
47 #define BLC_PWM_CTL _MMIO(0x61254)
69 #define BLC_HIST_CTL _MMIO(0x61260)
74 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
75 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
77 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
81 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
85 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
106 #define UTIL_PIN_CTL _MMIO(0x48400)
H A Dintel_fdi_regs.h11 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
13 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
14 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
15 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
16 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
17 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
19 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
148 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
149 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
H A Dintel_gmbus_regs.h13 #define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
30 #define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
40 #define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
57 #define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
67 #define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
70 #define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
78 #define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
H A Dintel_hdcp_regs.h14 #define HDCP_KEY_CONF _MMIO(0x66c00)
18 #define HDCP_KEY_STATUS _MMIO(0x66c04)
24 #define HDCP_AKSV_LO _MMIO(0x66c10)
25 #define HDCP_AKSV_HI _MMIO(0x66c14)
28 #define HDCP_REP_CTL _MMIO(0x66d00)
59 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
60 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
61 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
62 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
63 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
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H A Dintel_dp_aux_regs.h28 #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \
38 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
80 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
82 #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \
87 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
92 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
102 #define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
H A Dvlv_dsi_pll_regs.h11 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
13 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
18 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
81 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
105 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dreg.h69 (_MMIO(0x50090))) : \
71 (_MMIO(0x50098))) : \
73 (_MMIO(0x5009C))) : \
74 (_MMIO(0x50080))))); })
116 #define PCH_GMBUS0 _MMIO(0xc5100)
117 #define PCH_GMBUS1 _MMIO(0xc5104)
118 #define PCH_GMBUS2 _MMIO(0xc5108)
119 #define PCH_GMBUS3 _MMIO(0xc510c)
120 #define PCH_GMBUS4 _MMIO(0xc5110)
126 #define TRVADR _MMIO(0x4df0)
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H A Dhandlers.c728 _MMIO(0xd80),
735 _MMIO(0x2690),
736 _MMIO(0x2694),
737 _MMIO(0x2698),
738 _MMIO(0x2754),
739 _MMIO(0x28a0),
740 _MMIO(0x4de0),
741 _MMIO(0x4de4),
742 _MMIO(0x4dfc),
744 _MMIO(0x7014),
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