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Searched refs:_MASKED_BIT_ENABLE (Results 1 – 25 of 28) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c445 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in bdw_init_clock_gating()
507 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
511 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
513 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in ivb_init_clock_gating()
547 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); in vlv_init_clock_gating()
582 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in chv_init_clock_gating()
653 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
664 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
679 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); in i85x_init_clock_gating()
689 _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D)); in i85x_init_clock_gating()
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H A Di915_reg_defs.h204 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
H A Di915_perf.c2829 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
2872 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in gen12_enable_metric_set()
2874 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING)); in gen12_enable_metric_set()
2879 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen12_enable_metric_set()
4489 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
4497 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
H A Dintel_uncore.c130 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dreg.h94 (((_val) & _MASKED_BIT_ENABLE(_b)) == _MASKED_BIT_ENABLE(_b))
H A Dmmio_context.c474 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
H A Dhandlers.c2038 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
2041 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
2143 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2525 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_execlist.c51 u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); in __start_lrc()
65 _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); in __start_lrc()
87 ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); in __start_lrc()
H A Dxe_hw_engine.c330 u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE); in xe_hw_engine_enable_ring()
334 _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE)); in xe_hw_engine_enable_ring()
341 ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE); in xe_hw_engine_enable_ring()
H A Dxe_lrc.c574 regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in set_context_control()
579 _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE); in set_context_control()
1087 _MASKED_BIT_ENABLE(CTX_CTRL_RUN_ALONE)); in xe_lrc_init()
1092 _MASKED_BIT_ENABLE(CTX_CTRL_PXP_ENABLE)); in xe_lrc_init()
H A Dxe_eu_stall.c420 write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP); in clear_dropped_eviction_line_bit()
652 _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); in xe_eu_stall_stream_enable()
H A Dxe_pxp.c327 u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : in kcr_pxp_set_status()
H A Dxe_oa.c1073 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); in xe_oa_enable_metric_set()
1075 _MASKED_BIT_ENABLE(DISABLE_DOP_GATING)); in xe_oa_enable_metric_set()
1090 _MASKED_BIT_ENABLE(oa_debug) | in xe_oa_enable_metric_set()
H A Dxe_uc_fw.c837 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_rc6.c376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in chv_rc6_enable()
401 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in vlv_rc6_enable()
761 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
771 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
H A Dintel_ggtt_fencing.c918 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
922 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
926 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
H A Dintel_ring_submission.c128 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
172 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in set_pp_dir()
712 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
761 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
1048 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
H A Dintel_workarounds.c301 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
307 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
651 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), in icl_ctx_workarounds_init()
1107 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), in hsw_gt_workarounds_init()
2248 _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), in rcs_engine_wa_init()
2663 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2679 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2879 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), in general_render_compute_wa_init()
H A Dintel_lrc.c848 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH); in init_common_regs()
857 ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE); in init_common_regs()
1346 *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE); in gen12_invalidate_state_cache()
H A Dintel_engine_cs.c1238 engine->tlb_inv.request = _MASKED_BIT_ENABLE(val); in intel_engine_init_tlb_invalidation()
1633 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in __intel_engine_stop_cs()
1641 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); in __intel_engine_stop_cs()
2556 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); in xehp_enable_ccs_engines()
H A Dgen6_ppgtt.c70 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
H A Dintel_reset.c592 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
H A Dintel_execlists_submission.c2931 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2933 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
/linux-6.15/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp.c67 u32 val = enable ? _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) : in kcr_pxp_set_status()
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc_fw.c1116 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()

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