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Searched refs:X86_PMC_IDX_MAX (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/arch/x86/events/
H A Dperf_event.h53 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
133 struct perf_event *owners[X86_PMC_IDX_MAX];
134 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
209 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
253 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
254 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
265 u64 tags[X86_PMC_IDX_MAX];
268 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
711 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
809 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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H A Dcore.c230 i = X86_PMC_IDX_MAX; in reserve_pmc_hardware()
270 for_each_set_bit(i, cntr_mask, X86_PMC_IDX_MAX) { in check_hw_exists()
289 for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) { in check_hw_exists()
884 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { in __perf_sched_find_counter()
1372 DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1454 int assign[X86_PMC_IDX_MAX]; in x86_pmu_add()
1574 for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) { in perf_event_print_debug()
2283 int assign[X86_PMC_IDX_MAX]; in x86_pmu_commit_txn()
2490 if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX)) in perf_clear_dirty_counters()
2493 for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) { in perf_clear_dirty_counters()
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/linux-6.15/arch/x86/kvm/
H A Dpmu.c497 DECLARE_BITMAP(bitmap, X86_PMC_IDX_MAX); in kvm_pmu_handle_event()
502 bitmap_copy(bitmap, pmu->reprogram_pmi, X86_PMC_IDX_MAX); in kvm_pmu_handle_event()
730 bitmap_zero(pmu->reprogram_pmi, X86_PMC_IDX_MAX); in kvm_pmu_reset()
776 bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX); in kvm_pmu_refresh()
807 DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX); in kvm_pmu_cleanup()
813 pmu->pmc_in_use, X86_PMC_IDX_MAX); in kvm_pmu_cleanup()
822 bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX); in kvm_pmu_cleanup()
865 DECLARE_BITMAP(bitmap, X86_PMC_IDX_MAX); in kvm_pmu_trigger_event()
870 BUILD_BUG_ON(sizeof(pmu->global_ctrl) * BITS_PER_BYTE != X86_PMC_IDX_MAX); in kvm_pmu_trigger_event()
873 bitmap_copy(bitmap, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX); in kvm_pmu_trigger_event()
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H A Dpmu.h93 for_each_set_bit(i, bitmap, X86_PMC_IDX_MAX) \
243 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) in reprogram_counters()
/linux-6.15/arch/x86/events/amd/
H A Dcore.c305 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
306 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
435 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in __amd_put_nb_event_constraints()
547 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_alloc_nb()
740 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_check_overflow()
760 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_enable_all()
984 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_v2_handle_irq()
/linux-6.15/arch/x86/events/intel/
H A Dp4.c923 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_disable_all()
987 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(X86_PMC_IDX_MAX)], p4_running);
1002 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_enable_all()
1044 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_handle_irq()
1243 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; in p4_pmu_schedule_events()
1253 bitmap_zero(used_mask, X86_PMC_IDX_MAX); in p4_pmu_schedule_events()
1399 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_init()
H A Dknc.c242 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { in knc_pmu_handle_irq()
H A Dds.c2481 for_each_set_bit(bit, (unsigned long *)&pebs_enabled, X86_PMC_IDX_MAX) { in intel_pmu_pebs_event_update_no_drain()
2646 for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) { in intel_pmu_drain_pebs_icl()
2661 for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) { in intel_pmu_drain_pebs_icl()
H A Dcore.c3032 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { in x86_pmu_handle_guest_pebs()
3142 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { in handle_pmi_common()
3682 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { in intel_get_excl_constraints()
3734 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); in intel_get_event_constraints()
4421 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
4454 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_pmu_enable_all()
4956 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); in intel_cpuc_prepare()
H A Dlbr.c952 int i, j, pos = 0, order[X86_PMC_IDX_MAX]; in intel_pmu_lbr_counters_reorder()
/linux-6.15/arch/x86/include/asm/
H A Dperf_event.h15 #define X86_PMC_IDX_MAX 64 macro
H A Dkvm_host.h574 DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
577 DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
578 DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c386 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { in zhaoxin_pmu_handle_irq()