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Searched refs:X86_CONFIG (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/arch/x86/kernel/cpu/resctrl/
H A Dpseudo_lock.c1094 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in resctrl_arch_measure_l2_residency()
1096 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in resctrl_arch_measure_l2_residency()
1133 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in resctrl_arch_measure_l3_residency()
1135 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in resctrl_arch_measure_l3_residency()
/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c570 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
573 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
/linux-6.15/arch/x86/events/intel/
H A Dcore.c3847 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
4755 X86_CONFIG(.event=0xc0, .umask=0x01); in erratum_hsw11()
6528 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init_glc()
6723 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6726 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6907 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6910 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6947 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6950 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6988 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
/linux-6.15/arch/x86/events/
H A Dperf_event.h670 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro