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Searched refs:WREG32_SOC15_RLC (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c97 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
99 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
102 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
115 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
120 WREG32_SOC15_RLC( in gfxhub_v1_0_init_system_aperture_regs()
171 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
188 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
193 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
205 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
215 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); in gfxhub_v1_0_init_cache_regs()
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H A Dgfxhub_v1_2.c133 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0); in gfxhub_v1_2_xcc_init_system_aperture_regs()
135 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_2_xcc_init_system_aperture_regs()
139 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_2_xcc_init_system_aperture_regs()
152 WREG32_SOC15_RLC(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_system_aperture_regs()
157 WREG32_SOC15_RLC(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_system_aperture_regs()
216 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_init_tlb_regs()
237 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
242 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
254 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
265 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp); in gfxhub_v1_2_xcc_init_cache_regs()
[all …]
H A Damdgpu_amdkfd_gc_9_4_3.c309 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
344 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
351 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, in kgd_gfx_v9_4_3_hqd_load()
355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
H A Dmmhub_v2_0.c207 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
209 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
212 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
214 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
225 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
226 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v2_0_init_system_aperture_regs()
227 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v2_0_init_system_aperture_regs()
334 WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp); in mmhub_v2_0_enable_system_domain()
H A Dgfx_v9_4_3.c713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_ind()
725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, in wave_read_regs()
1282 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1284 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1291 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1299 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_constants_init()
1688 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, in gfx_v9_4_3_xcc_cp_compute_enable()
1941 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, in gfx_v9_4_3_xcc_kiq_init_register()
1956 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1960 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, in gfx_v9_4_3_xcc_kiq_init_register()
[all …]
H A Damdgpu_amdkfd_gfx_v9.c94 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load()
277 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_hqd_load()
279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load()
281 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_hqd_load()
283 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_hqd_load()
285 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_hqd_load()
290 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR, in kgd_gfx_v9_hqd_load()
294 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data); in kgd_gfx_v9_hqd_load()
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H A Dgfx_v9_0.c1931 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
1943 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
3233 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
3436 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable()
3438 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
3685 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, in gfx_v9_0_kiq_init_register()
3694 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v9_0_kiq_init_register()
3700 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, in gfx_v9_0_kiq_init_register()
3704 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, in gfx_v9_0_kiq_init_register()
3706 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, in gfx_v9_0_kiq_init_register()
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H A Dsoc15_common.h172 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ macro
H A Dgfx_v10_0.c5415 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, in gfx_v10_0_init_csb()
5417 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, in gfx_v10_0_init_csb()
5419 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
6044 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()