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Searched refs:WREG32_SOC15_IP (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c258 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, in sdma_v7_0_ring_set_wptr()
262 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, in sdma_v7_0_ring_set_wptr()
534 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v7_0_gfx_resume_instance()
609 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v7_0_gfx_resume_instance()
617 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); in sdma_v7_0_gfx_resume_instance()
624 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp); in sdma_v7_0_gfx_resume_instance()
747 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); in sdma_v7_0_load_microcode()
749 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), in sdma_v7_0_load_microcode()
751 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), in sdma_v7_0_load_microcode()
756 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); in sdma_v7_0_load_microcode()
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H A Dsdma_v6_0.c230 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
233 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
468 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume_instance()
517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); in sdma_v6_0_gfx_resume_instance()
586 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v6_0_gfx_resume_instance()
595 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); in sdma_v6_0_gfx_resume_instance()
602 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); in sdma_v6_0_gfx_resume_instance()
770 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); in sdma_v6_0_soft_reset()
774 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); in sdma_v6_0_soft_reset()
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H A Dsdma_v5_2.c479 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
481 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume_instance()
570 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume_instance()
571 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume_instance()
572 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume_instance()
590 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), in sdma_v5_2_gfx_resume_instance()
592 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), in sdma_v5_2_gfx_resume_instance()
649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume_instance()
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H A Dsdma_v5_0.c426 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
429 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
666 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
668 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
670 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
751 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume_instance()
752 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume_instance()
753 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume_instance()
754 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume_instance()
778 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), in sdma_v5_0_gfx_resume_instance()
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H A Dsoc15_common.h86 #define WREG32_SOC15_IP(ip, reg, value) \ macro
H A Dgfx_v12_0.c1818 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v12_0_enable_gui_idle_interrupt()
4652 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4660 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4703 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4711 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4823 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4837 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4869 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4883 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_inst_fault_state()
H A Dgfx_v11_0.c2146 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
6193 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6201 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6250 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6258 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6370 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6384 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6416 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6430 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6568 WREG32_SOC15_IP(GC, target, tmp);
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H A Damdgpu_gmc.c951 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
952 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
H A Damdgpu_amdkfd_gfx_v10_3.c214 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3()
H A Dgfx_v10_0.c5403 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
9059 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9065 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9112 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9118 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9227 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_priv_reg_fault_state()
9241 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_priv_reg_fault_state()
9273 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_bad_op_fault_state()
9287 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_bad_op_fault_state()
9416 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
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H A Dgmc_v9_0.c509 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
537 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
H A Damdgpu_amdkfd_gfx_v10.c228 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
H A Dsoc15.c500 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); in soc15_program_register_sequence()
H A Dgfx_v9_0.c6008 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6014 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6070 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6106 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()