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Searched refs:WREG32_SOC15_DPG_MODE_1_0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c467 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, in vcn_v1_0_mc_resume_dpg_mode()
1043 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1047 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, in vcn_v1_0_start_dpg_mode()
1063 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, in vcn_v1_0_start_dpg_mode()
1066 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, in vcn_v1_0_start_dpg_mode()
1072 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v1_0_start_dpg_mode()
1078 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v1_0_start_dpg_mode()
1092 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, in vcn_v1_0_start_dpg_mode()
1097 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1102 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, in vcn_v1_0_start_dpg_mode()
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H A Damdgpu_vcn.h90 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ macro