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Searched refs:WREG32_FIELD15_PREREG (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c184 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_3_init_system_aperture_regs()
392 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_3_gart_disable()
H A Dgfxhub_v3_0.c179 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_init_system_aperture_regs()
399 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
H A Dgfxhub_v11_5_0.c183 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v11_5_0_init_system_aperture_regs()
402 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v11_5_0_gart_disable()
H A Dnbio_v7_9.c236 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v7_9_enable_doorbell_aperture()
388 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, in nbio_v7_9_enable_doorbell_interrupt()
H A Dgfxhub_v12_0.c187 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v12_0_init_system_aperture_regs()
407 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v12_0_gart_disable()
H A Dgfx_v9_4_3.c352 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); in gfx_v9_4_3_init_golden_registers()
1329 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v9_4_3_xcc_enable_save_restore_machine()
1475 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1492 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1495 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, in gfx_v9_4_3_xcc_rlc_reset()
1511 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
1916 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_kiq_init_register()
2278 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v9_4_3_xcc_fini()
3108 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_priv_reg_fault_state()
3148 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v9_4_3_set_bad_op_fault_state()
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H A Dsoc15_common.h58 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ macro
H A Dnbif_v6_3_1.c158 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbif_v6_3_1_enable_doorbell_aperture()
H A Dnbio_v4_3.c154 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, in nbio_v4_3_enable_doorbell_aperture()
H A Damdgpu_amdkfd_gfx_v11.c501 WREG32_FIELD15_PREREG(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in hqd_destroy_v11()
H A Dgfx_v12_0.c1731 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v12_0_constants_init()
1847 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v12_0_rlc_reset()
1849 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v12_0_rlc_reset()
1882 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_0_rlc_start()
3159 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v12_0_kiq_init_register()
3253 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c2047 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
2175 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2177 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2210 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
4273 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4367 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()