| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges() 363 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges() 367 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn316_build_watermark_ranges() 370 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn316_build_watermark_ranges() 373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn316_build_watermark_ranges() 378 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges() 379 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges() 390 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn316_build_watermark_ranges() 391 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges() 392 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn316_build_watermark_ranges() [all …]
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| H A D | dcn316_smu.h | 56 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges() 401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges() 405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges() 408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges() 411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in vg_build_watermark_ranges() 416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges() 417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges() 428 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in vg_build_watermark_ranges() 429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges() 430 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in vg_build_watermark_ranges() [all …]
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| H A D | dcn301_smu.h | 71 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges() 437 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges() 441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges() 444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges() 447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges() 452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges() 453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges() 464 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges() 465 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges() 466 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn31_build_watermark_ranges() [all …]
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| H A D | dcn31_smu.h | 68 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges() 398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges() 402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn315_build_watermark_ranges() 405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn315_build_watermark_ranges() 408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn315_build_watermark_ranges() 413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges() 414 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges() 425 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn315_build_watermark_ranges() 426 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges() 427 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn315_build_watermark_ranges() [all …]
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| H A D | dcn315_smu.h | 57 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 500 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges() 501 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges() 505 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges() 508 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges() 511 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn314_build_watermark_ranges() 516 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges() 517 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges() 528 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn314_build_watermark_ranges() 529 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges() 530 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn314_build_watermark_ranges() [all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 755 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges() 756 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges() 760 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn35_build_watermark_ranges() 763 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn35_build_watermark_ranges() 766 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn35_build_watermark_ranges() 771 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges() 772 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges() 783 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; in dcn35_build_watermark_ranges() 784 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn35_build_watermark_ranges() 785 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; in dcn35_build_watermark_ranges() [all …]
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| H A D | dcn35_smu.h | 65 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu10_driver_if.h | 65 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu13_driver_if_v13_0_5.h | 67 WM_DCFCLK, enumerator
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| H A D | smu13_driver_if_yellow_carp.h | 66 WM_DCFCLK, enumerator
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| H A D | smu12_driver_if.h | 67 WM_DCFCLK, enumerator
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| H A D | smu13_driver_if_v13_0_4.h | 67 WM_DCFCLK, enumerator
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| H A D | smu11_driver_if_vangogh.h | 66 WM_DCFCLK, enumerator
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| H A D | smu14_driver_if_v14_0_0.h | 62 WM_DCFCLK, enumerator
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 424 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table() 426 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table() 428 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table() 430 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table() 433 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
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| H A D | smu_v13_0_4_ppt.c | 678 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table() 680 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table() 682 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table() 684 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table() 687 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
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| H A D | yellow_carp_ppt.c | 515 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table() 517 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table() 519 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table() 521 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in yellow_carp_set_watermarks_table() 524 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 1079 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table() 1081 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table() 1083 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table() 1085 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table() 1088 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table() 1090 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 497 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table() 499 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v14_0_0_set_watermarks_table() 501 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v14_0_0_set_watermarks_table() 503 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v14_0_0_set_watermarks_table() 506 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v14_0_0_set_watermarks_table()
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| /linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 1613 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table() 1615 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table() 1617 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table() 1619 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in vangogh_set_watermarks_table() 1622 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in vangogh_set_watermarks_table()
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| /linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.c | 1373 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
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