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Searched refs:VSYNC (Results 1 – 25 of 35) sorted by relevance

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/linux-6.15/Documentation/admin-guide/media/
H A Dmgb4.rst100 The type of VSYNC pulses as detected by the video format detector.
120 If the incoming video signal does not contain synchronization VSYNC and
124 internal VSYNC pulse.
127 If the incoming video signal does not contain synchronization VSYNC and
150 Width of the VSYNC signal in PCLK clock ticks.
170 Number of video lines between deassertion of the VSYNC signal and the video
178 by DE=1) and assertion of the VSYNC signal.
247 VSYNC signal polarity.
272 Width of the VSYNC signal in video lines. The default value is 20.
284 Number of video lines between deassertion of the VSYNC signal and the video
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/linux-6.15/drivers/gpu/drm/nouveau/dispnv50/
H A Ddac507d.c38 sync |= NVVAL(NV507D, DAC_SET_POLARITY, VSYNC, asyh->or.nvsync); in dac507d_ctrl()
/linux-6.15/Documentation/devicetree/bindings/media/
H A Drenesas,vin.yaml92 If both HSYNC and VSYNC polarities are not specified, embedded
98 If both HSYNC and VSYNC polarities are not specified, embedded
141 If both HSYNC and VSYNC polarities are not specified, embedded
147 If both HSYNC and VSYNC polarities are not specified, embedded
H A Dvideo-interfaces.yaml124 Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. Note,
125 that if HSYNC and VSYNC polarities are not specified, embedded
132 Similar to HSYNC and VSYNC, specifies data line polarity.
138 Similar to HSYNC and VSYNC, specifies the data enable signal polarity.
/linux-6.15/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u11-smarc-du-adv7513.dtso49 <RZG2L_PORT_PINMUX(12, 0, 6)>; /* VSYNC */
/linux-6.15/Documentation/devicetree/bindings/media/i2c/
H A Dtvp514x.txt19 - vsync-active: VSYNC Polarity configuration for endpoint.
H A Dtvp7002.txt13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
H A Dov7670.txt14 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
H A Dtvp5150.txt45 - vsync-active: Active state of the VSYNC signal. Must be <1> (HIGH).
/linux-6.15/drivers/video/fbdev/i810/
H A Di810_regs.h153 #define VSYNC 0x60014 macro
/linux-6.15/Documentation/fb/
H A Dpxafb.rst45 vsynclen:VSYNC == LCCR2_VSW + 1
65 hsync:HSYNC, vsync:VSYNC
H A Dmatroxfb.rst265 upper:X top boundary: lines between end of VSYNC pulse and start of first
267 lower:X bottom boundary: lines between end of picture and start of VSYNC
269 vslen:X length of VSYNC pulse, in lines. Default is derived from `vesa`
279 sync:X sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
/linux-6.15/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml50 frame start (VSYNC), line flag and other status interrupts.
H A Drockchip-vop2.yaml46 sources, such as frame start (VSYNC), line flag and other interrupt status.
/linux-6.15/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos7-decon.yaml74 - description: VSYNC
H A Dsamsung,exynos5-dp.yaml60 VSYNC polarity configuration. High if defined, low if not defined
H A Dsamsung,fimd.yaml99 - description: VSYNC
/linux-6.15/include/video/
H A Dsstfb.h162 #define VSYNC 0x0224 macro
/linux-6.15/arch/arm/boot/dts/ti/omap/
H A Dam437x-sbc-t43.dts59 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
/linux-6.15/Documentation/userspace-api/media/drivers/
H A Dimx-uapi.rst94 Input capture requires hardware support. A VSYNC signal must be routed
/linux-6.15/drivers/gpu/drm/bridge/
H A Dchipone-icn6211.c53 #define VSYNC 0x28 macro
403 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start); in chipone_atomic_enable()
/linux-6.15/arch/arm/boot/dts/nxp/imx/
H A Dimx53-qsb-common.dtsi311 /* VGA_HSYNC, VSYNC with max drive strength */
H A Dimx6ul-tx6ul-mainboard.dts206 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
H A Dimx6ul-tx6ul.dtsi592 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
625 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
/linux-6.15/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc-compat.c81 PIS(VSYNC); in dispc_dump_irqs()

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