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Searched refs:VEBOX_RING_BASE (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h44 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
45 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
46 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
H A Dintel_rc6.c463 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) { in bxt_check_bios_rc6_setup()
H A Dintel_engine_cs.c198 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h27 #define VEBOX_RING_BASE 0x1c8000 macro
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c143 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
H A Dhandlers.c2179 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2808 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c50 MMIO_F(prefix(VEBOX_RING_BASE), s); \
1255 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
H A Di915_reg.h299 #define VEBOX_RING_BASE 0x1a000 macro
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c208 .mmio_base = VEBOX_RING_BASE,